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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

It does not? Dang it. I just moved all the code I needed for RRIP into its own .vhd file. I see what you mean though. I think that I am trying to keep as close as I can to the example, I saw in the Intel Reset Release IP video. It had the example I started with. I need to take that as pseudo code and work from there. What parts of the code (image attached) do I need to implement and what parts are already made in the IP itself? Am I declaring too many things? I think I am confusing many things together and am making too much code. Is there an example I can use of non-pseudocode?

Apologies for this taking a long time to get into my head, I think I keep focusing on the wrong thing.

Thank you,

Drew

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
You didn't manage to write valid entity code for rr_ip and sys_pll. Apart from other details, the entity name has to match the instantiated name. E.g.
entity rr_ip ...