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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

Alright, I think I took care of that issue, but now something new has happened. I am getting an error saying that the IP may not work with my code. Did I turn on the signals wrong, or does the IP need to be its own VHDL file? I am attaching my code for review and the errors.

Thank you,

Drew

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
The error message tells you that your project misses implementation code for the two instantiated components.