Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Regular ContributorHi Drew,
I think you can ignore the Evaluation Mode warning. It doesn't seem like you're using it anyway. More info about it here: https://www.intel.com/content/www/us/en/docs/programmable/683502/17-1/an-320-using.html
You got those warnings because the reset release IP isn't connected to those registers, and in fact it isn't connected to anything in your project at all. I wasn't sure how you want to connect the reset release IP and I'm not an expert on this IP's usage. I was just helping out to fix the syntax errors.
What do you want to use this IP for? How do you want to connect it to the other modules?
You may find this useful: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/archives/an891-19-3.pdf
Regards,
Nurina
MATRIX7878Hello,
I can ignore them? Good to know.
It is not connected, but it is included. I see, I will need to see how to actually use it. The only reason I even knew about the RRIP was because I got a critical warning about it. Other than that, the project was fine. I appreciate the help with the syntax errors.
I am using the IP to reset the FPGA after the circuit is programmed. I am not sure how I want to connect it to other modules. I thought that maybe it would connect itself as the IP was connected.
It seems like I need to go more in depth into that .pdf.
Thank you,
Drew
