Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Super ContributorO.k., resetRelease.vhd (second screenshot) contains entity declaration, but many syntax errors. Obviously it has been never compiled.
Not intended to be exhaustive:
- each entity declaration needs its own library statement
- all signals used in the arcitecture must be declared, either as port or internal signal
- process needs begin statement
- signal assignment uses <= rather than => operator
- can't write port signals with direction "in"
It seems to me that you filled architecture bodies with arbitrary signal assignments instead of implementing meaningful code function. I'd rather try to write entities that serve a useful purpose.
