Forum Discussion

MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


I checked and it's because toplevel.vhd is not set as top level entity.

Set the toplevel.vhd as top level entity and it will resolve the RES-10204 - Reset Release Instance Count Check warning.


Ultimately you should check the RTL viewer/simulation to see if this is the circuit/functionality you were going for.


Regards,

Nurina


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

That solves that problem, but there is the other error that I am attaching below. I do not know why it says that the FPGA is not compatible. It sounds to me that either the FPGA cannot get out of the RRIP, or it cannot find the registers to get in. I am not sure which, if either. That should be the last thing I need help with.

Thank you,

Drew