Forum Discussion
MATRIX7878
Occasional Contributor
Occasional ContributorReset Release IP VHDL code not working
Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
FvM
Super Contributor
Super ContributorRegarding your other question, you don't necessarily need compoenent decalarations when instantiating VHDL entities, you can use
this syntax
u1: entity work.sys_pll instead of u1: sys_pll
Alos explained in the links given by Nurina
