Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Regular ContributorHi,
Now your Reset Release IP VHDL file does not look like Reset Release IP at all.
Are the reset release IP and sys_pll the same? Why are you combining them?
The error message is saying that you need to have an entity for both RRIP and sys_pll.
You may find these useful:
https://fpgatutorial.com/vhdl-entity-architecture-library/
https://vhdlwhiz.com/entity-instantiation-and-component-instantiation/
https://nandland.com/entity-and-architecture/
Regards,
Nurina
MATRIX7878Hello,
It does not? Dang it. I just moved all the code I needed for RRIP into its own .vhd file. I see what you mean though. I think that I am trying to keep as close as I can to the example, I saw in the Intel Reset Release IP video. It had the example I started with. I need to take that as pseudo code and work from there. What parts of the code (image attached) do I need to implement and what parts are already made in the IP itself? Am I declaring too many things? I think I am confusing many things together and am making too much code. Is there an example I can use of non-pseudocode?
Apologies for this taking a long time to get into my head, I think I keep focusing on the wrong thing.
Thank you,
Drew
FvMSuper Contributor
You didn't manage to write valid entity code for rr_ip and sys_pll. Apart from other details, the entity name has to match the instantiated name. E.g.
entity rr_ip ...
