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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Drew,


Since this involves a few vhd files, can you share the .qar file of your project?

To generate this, go to Project>Archive project.


This is so that I can add the necessary code changes and you can review them.


Regards,

Nurina


  • MATRIX7878's avatar
    MATRIX7878
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Of course. Please find attached my .qar for this project. The project itself is so much easier than the RRIP part. At least it seems to be. I have yet to comment the code, but thanks to the structure of VHDL, it seems to be more self-explanatory.

    Thank you,

    Drew