Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Regular ContributorHi Drew,
Here is the .qar file with resolved code as promised.
You can check the RTL viewer to see if the connections were what you were intending.
I highly recommend these training videos since you're a beginner:
https://www.youtube.com/watch?v=bwoyQ_RnaiA&
https://www.youtube.com/watch?v=lHowLUNHFFA&
The VHDL training link shared by strell is also very useful to go through.
Regards,
Nurina
Occasional ContributorHello,
It looks good in the RTL viewer. Will need to run a simulation of course to make sure it works. I am currently enrolled in the Intel training versions of those YouTube links you shared.
While all the errors are gone, upon completing the Analysis and Synthesis step of compilation, I get the warnings attached in the image. I look at the file that the 2nd warning references and it complains that the Reset Release is not there. I'm confused. Is the IP not started? What do I need to do? I am attaching the report file as well. We were so close to me getting it. Is it because I am using an Agilex 7 M-Series? I would not see why.
Thank you for your continued support. It means a lot to me.
Drew
