Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Regular ContributorHello,
Seems to me that the Reset Release IP is correctly instantiated.
Based on the error message, the problem is due to the sys_pll component instantiation on line 26.
You were trying to connect to ports that do not exist in the sys_pll component.
Please check if the connections are correct. These threads may be helpful for you: https://www.edaboard.com/threads/problem-with-using-components-in-vhdl.374664/
Regards,
Nurina
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorHello,
Alright, I think I took care of that issue, but now something new has happened. I am getting an error saying that the IP may not work with my code. Did I turn on the signals wrong, or does the IP need to be its own VHDL file? I am attaching my code for review and the errors.
Thank you,
Drew
FvMSuper Contributor
The error message tells you that your project misses implementation code for the two instantiated components.
