Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Super ContributorHi,
the message tells about VHDL syntax errors, a bit different from "not working".
It's generally a good idea to fix syntax errors from top to bottom, succeeding erors may be just aftereffects.
First errors are incorrect component declarations.
Component declarations follows this scheme
component_declaration ::=
component identifier [ is ]
[ local_generic_clause ]
[ local_port_clause ]
end component [ component_simple_name ] ;
There's no place for signals in component declaration.
You'll later notice that your component declaration, besides unexpected signal declaration are also incomplete because they don't
declare all ports of the respective components.
We would e.g. expect
component rr_ip
port(
ninit_done : out std_logic
);
end component;
Just to give you a starting point. You should have a VHDL text book or tutorial at hand.
Occasional ContributorHello,
Ok, I see where I am going wrong. I still do not know where to (or rather what to declare) some of the variables as. I have tried to figure out what I need to do for the Reset Release IP but cannot get it to work. I do not know what should be a signal, a port, or something else. I am attaching my new code and errors. The Reset Release code is lines 13-27. I hope this looks better. I have tried to follow the tutorial for the Reset Release IP I found through Intel, but the code provided was pseudocode and I am still trying to figure out VHDL.
Thank you,
Drew
