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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Drew,


Is the sys_pll suppose to be just a PLL? Where did you get this code?

Based on line 15, you are latching the sys_rst with locked and rst but there is a syntax error due to locked being an output port of the sys_pll. I'm not sure what you wanted the sys_pll to describe.


I have resolved the errors and used an IOPLL IP in place of the sys_pll.vhd. You can make changes to the IOPLL settings as you wish. I'm attaching the .qar file here shortly.


Regards,

Nurina


MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

I got this code from the Reset Release IP video I found on Intel's website and also on YouTube. I was following the code that I saw on that video to get the sys_rst line.

You used another IP? Ok.

Thank you,

Drew