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Vigneswaran's avatar
Vigneswaran
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3 hours ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt

 

In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?

 

2 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 hours ago

    Hi,

    I'd refer to Agilex 7 datasheet TDS I/O standard specification. With Vccio of 1.5 V, Vicm of up to 1.4 V is supported. In other words, standard LVDS peer is o.k. With Vccio of 1.2 V, a level shifting means (e.g. voltage divider) or AC coupling would be required.

    Regards Frank

  • Vigneswaran's avatar
    Vigneswaran
    Icon for New Member rankNew Member
    2 hours ago

    Thanks for your reply.

    Common mode is not a problem for me. The differential is the problem. You have given , for Vicm = 1.4V , I can have swing of Vid = 100mV only. But in my secondary chips , the given Vocm = 1.375 , but swing is 400mV. So if you calculate the voltage peak , V = Vcm+(Vid/2) , so V=1.375+(400/2) , which is 1.575V. Now since it exceeded the threshold of 1.5V mentioned in datasheet of FPGA , will this fail in my circuit? means does the FPGA cannot capture it correctly?