LVDS support on Agilex 7

Hi,

I'd refer to Agilex 7 datasheet TDS I/O standard specification. With Vccio of 1.5 V, Vicm of up to 1.4 V is supported. In other words, standard LVDS peer is o.k. With Vccio of 1.2 V, a level shifting means (e.g. voltage divider) or AC coupling would be required.

Regards Frank

Thanks for your reply.

Common mode is not a problem for me. The differential is the problem. You have given , for Vicm = 1.4V , I can have swing of Vid = 100mV only. But in my secondary chips , the given Vocm = 1.375 , but swing is 400mV. So if you calculate the voltage peak , V = Vcm+(Vid/2) , so V=1.375+(400/2) , which is 1.575V. Now since it exceeded the threshold of 1.5V mentioned in datasheet of FPGA , will this fail in my circuit? means does the FPGA cannot capture it correctly?

Hi,

what do you mean with "1.5 V threshold"? Please review the TDS I/O standard specification:

Your driver specification (= standard LVDS) is within specified range.

Regards
Frank

P.S.: 1.5 V GPIO absolute maximum Vi rating is 1.7 V. Above specified Vicm + Vid/2 relates to Vi,max of 1.7 V. 

Hi!

Thanks for your quick response.

The absolute max specification of LVDS 1.5V powered IO bank is mentioned as 1.7V.

As you have stated, if VICM is 1.4 and VID is 600mV then my VOH will be 1.7V which is the absolute max rating right? is there no headroom between ABS max and recommended max?

I am planning to interface DS90LV804TSQ with Agilex, its specification mentions, VOD max as 600mV and Vos max as 1.475V which would bring my VOH to 1.775, will it not exceed Agilex specification or can i use the same part?

Thanks in-advance,

Vigneswaran

Hi Vigneswaran,

you are right, DS90LV804 driver is at risk to exceed Agilex 7 absolute ratings due to larger Vocm tolerances. It should be also considered that on-chip rd termination is disabled in unconfigured FPGA state, resulting in even higher initial Vid. To keep on the safe side, I would either use a driver chip with tighter Vocm tolerance, add resistors that pull down common mode level or implement voltage dividers that shift signal level towards ground.

Regards
Frank

Hi Frank,

Thanks, I will change the part with tighter Vocm.

"As you have stated, if VICM is 1.4 and VID is 600mV then my VOH will be 1.7V which is the absolute max rating right? is there no headroom between ABS max and recommended max?"

1)Is there no headroom between ABS max and recommended max? can i select new part with VICM is 1.4 and VID is 600mV or select a part with headroom? if so how much headroom shall i implement for safer design?

 "on-chip rd termination is disabled in unconfigured FPGA state, resulting in even higher initial Vid"

2)I am planning to provide LVDS clock from SI5391 which brings my VOH to 1.5V. once power is provided, clock output will be present during unconfigured FPGA state, what will be the increase in VID swing on-chip rd termination ? will it damage my IC?

3) I also went through the 80-0330678-D1(AGILEX 7 F-Series FPGA Development Kit), where clock is provided from ZL30733LDG1Q089 IC without any voltage shifting/dividing. How higher initial Vid due to disabled on-chip rd termination during unconfigured FPGA is handled? 

Thanks in-advance,

Vigneswaran

Hi frank,

Also clear my another doubt, as mentioned in power budget topic , what is the maximum power consumption per rail. So that i can calculate my scaling factor.

Thanks,

Vigneswaran

Hi Vigneswaran,

regarding Si5391 interfacing with TDS 1.5 I/O standard, I think that VDD of 1.8 V (sub-LVDS with Vocm of 0.9 V) will better fit Agilex 5.

As for power supply requirements, they strongly depend on clock frequency and switching activity. Therefore Quartus final power estimation is performed for a synthesiszed design.

Regards
Frank

Hi Frank,

Can you please elaborate the below queries in sequence,  

1)Is there no headroom between ABS max and recommended max? can i select new part with VICM is 1.4 and VID is 600mV or select a part with headroom? if so how much headroom shall i implement for safer design?

2) SI5391 with VOH 1.5V falls within the acceptable limit of  TDS 1.5 I/O standard. Why is it not suitable? If so, what is the preffered chip for Agilex 7?

3) once power is provided, clock output will be present during unconfigured FPGA state, what will be the increase in VID swing with on-chip rd termination disabled? will it damage my IC?

4) I also went through the 80-0330678-D1(AGILEX 7 F-Series FPGA Development Kit), where clock is provided from ZL30733LDG1Q089 IC without any voltage shifting/dividing. How higher initial Vid due to disabled on-chip rd termination during unconfigured FPGA is handled?

5) Yes , i have got my power estimate from quartus prime based on our requirement which is "  board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , which value should i consider?

Appreciate your efforts,

Vigneswaran 

Hi Vigneswaran,

I think, you don't need additional margin for datasheet specifications of maximal Vicm and Vid. We can assume that the specificatons are well considered. Possible exeedance during power on should be however avoided. I'd assume that unterminated LVDS driver can have a least doubled voltage swing, worst case up to supply rails. If this is critical, you should use external instead of programmed internal termination. 

Regarding ZL30733 usage on Altera Development Kits, I can't determine if it keeps maximum Agilex 7 ratings, I don't have a device datasheet. According to product brief, output Vocm is programmable and has factory configurable power-on configuration. So it might use safe parameters. Said device kit is however using VDD of 1.2V for GPIO banks containing respective TDS clock inputs, thus limits are lower than discussed for 1.5V TDS.

Regards
Frank