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Vigneswaran's avatar
Vigneswaran
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4 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
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Core Logic
Programmable Logic Device
Vigneswaran's avatar
Vigneswaran
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4 months ago

Thanks for your reply.

Common mode is not a problem for me. The differential is the problem. You have given , for Vicm = 1.4V , I can have swing of Vid = 100mV only. But in my secondary chips , the given Vocm = 1.375 , but swing is 400mV. So if you calculate the voltage peak , V = Vcm+(Vid/2) , so V=1.375+(400/2) , which is 1.575V. Now since it exceeded the threshold of 1.5V mentioned in datasheet of FPGA , will this fail in my circuit? means does the FPGA cannot capture it correctly?