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Vigneswaran's avatar
Vigneswaran
Icon for New Contributor rankNew Contributor
4 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
Configuration
Core Logic
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 months ago

Hi,

what do you mean with "1.5 V threshold"? Please review the TDS I/O standard specification:

Your driver specification (= standard LVDS) is within specified range.

Regards
Frank

P.S.: 1.5 V GPIO absolute maximum Vi rating is 1.7 V. Above specified Vicm + Vid/2 relates to Vi,max of 1.7 V.