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Vigneswaran's avatar
Vigneswaran
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2 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
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Core Logic
Programmable Logic Device
Vigneswaran's avatar
Vigneswaran
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2 months ago

Hi Frank,

Thanks, I will change the part with tighter Vocm.

"As you have stated, if VICM is 1.4 and VID is 600mV then my VOH will be 1.7V which is the absolute max rating right? is there no headroom between ABS max and recommended max?"

1)Is there no headroom between ABS max and recommended max? can i select new part with VICM is 1.4 and VID is 600mV or select a part with headroom? if so how much headroom shall i implement for safer design?

 "on-chip rd termination is disabled in unconfigured FPGA state, resulting in even higher initial Vid"

2)I am planning to provide LVDS clock from SI5391 which brings my VOH to 1.5V. once power is provided, clock output will be present during unconfigured FPGA state, what will be the increase in VID swing on-chip rd termination ? will it damage my IC?

3) I also went through the 80-0330678-D1(AGILEX 7 F-Series FPGA Development Kit), where clock is provided from ZL30733LDG1Q089 IC without any voltage shifting/dividing. How higher initial Vid due to disabled on-chip rd termination during unconfigured FPGA is handled? 

 

Thanks in-advance,

Vigneswaran