Regarding Power-Up Sequence for Agilex 5

Regarding the power sequencing of Agilex 5, the required power-up sequence is specified in the documentation. However, in our case, the sequence was not properly followed.

Could you please advise what kind of impact may occur on the FPGA if voltages are applied under such a condition where the specified power sequence is not met?

Power Management User Guide: Agilex 5 FPGAs and SoCs
https://docs.altera.com/viewer/book-attachment/PgABpvRJy7P6fU_ZAXzUJw/zAjQMZanXPEHuIot~~5CbA-PgABpvRJy7P6fU_ZAXzUJw