Forum Discussion

Vigneswaran's avatar
Vigneswaran
Icon for New Contributor rankNew Contributor
4 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
Configuration
Core Logic
Programmable Logic Device
Vigneswaran's avatar
Vigneswaran
Icon for New Contributor rankNew Contributor
4 months ago

Hi frank,

Also clear my another doubt, as mentioned in power budget topic , what is the maximum power consumption per rail. So that i can calculate my scaling factor.

Thanks,

Vigneswaran