Forum Discussion

Steve-Mowbray-ENL's avatar
Steve-Mowbray-ENL
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
Solved

How to tell Quartus my Arria10 target system CLKUSR frequency is 100MHz?

Timing analyser reports CLKUSR at 125MHz but target system has 100MHz on this pin to accommodate AS in combination with transceiver calibration as per the manuals -- there doesn't seem to be any consequences as the project seems to run fine but is a bit unsettling

Configuration
  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    2 months ago

    Hi Steve,

     

    Based on the response that I provided, you need not worry about the constraint on the pin for XCVRs.
    As the Quartus is assuming a 125MHz frequency, it is basically constraining it to the maximum allowed frequency for the XCVR applications. If the timing analyzer reports that 125MHz is achieved, then 100MHz will definitely work.

     

    Regards,
    Aqid

10 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 months ago

    Hi Steve,
    I'm not quite sure where 125 MHz comes from may be it's a default. You can include CLKUSR as top level pin in your design and assign 100 MHz clock in .sdc. The specification should be used for all instances of automatic "~ALTERA_CLKUSR~" signal in your design.

    Regards
    Frank


    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      3 months ago

      Thanks Frank -- seems straightforward -- couple of questions before I fire up quartus -- is there any consequences for being explicit on this pin -- also any chance this clock is useable in the user logic as this would be useful "free" clock source?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 months ago


    Hi Steve,
    pin connection guidelines say about clkusr pin

    This pin can be used as a GPIO pin only if you are not using
    transceivers, not using HMC, and not using this pin as a user
    supplied configuration clock.

    Regards
    Frank

    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      3 months ago

      Thanks Frank -- yes that is my understanding -- my concern is by explicitly assigning the CLKUSR pin does Quartus infer that the pin is now a GPIO pin thus excluding transceiver use -- doing a project build now so will hopefully have some Quartus reporting to discuss shortly. Regards Steve 

      UPDATE: build complete with interesting critical warning:

      Critical Warning (18326): The design pin 'clkusr' has been assigned to CLKUSR pin location 'Y15'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transceivers and certain IOs. If the pin 'clkusr' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'.

      So optimistic interpretation of the above implies that so long as clkusr pin has valid clock signal then transceivers will still calibrate correctly even when the global assignment is applied to suppress the critical warning... Digging through the Platform Designer synthesis files I found:

      (*altera_attribute = "-name SDC_STATEMENT \"if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }\"" *)

      in "altera_a10_xcvr_reset_sequencer_211\synth\alt_sld_fab_altera_a10_xcvr_reset_sequencer_211_33t7nri.v"

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi, 

    Can you try this : remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'.

    regards,
    Farabi

    • Steve-Mowbray-ENL's avatar
      Steve-Mowbray-ENL
      Icon for Occasional Contributor rankOccasional Contributor
      3 months ago

      Hi Farabi

      Rather than experimenting with cludge fixes I am focussing on the Platform Designer automatic generated:

      (*altera_attribute = "-name SDC_STATEMENT \"if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }\"" *)

      associated with the transceiver reset sequencer instance in the design -- doesn't seem to be an obvious IP parameter to tell the instance that CLKUSR is at 100MHz rather than 125MHz...

      Transceiver PHY Reset Controller (parameters)

      Regards, Steve

      • AqidAyman_Altera's avatar
        AqidAyman_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 months ago

        Hi Steve,

         

        Please refer to the following explanation of the Warning that you see.

        https://microsites.altera.com/microsites/psg_microsites_migration/quartushelp/current/index.htm#msgs/msgs/wcio_design_pin_assigned_to_clkusr_location.htm 

         

        Based on the explanation, we would infer that Quartus detected transceivers in your design.

        • If transceivers are used in your design, then you need NOT do a pin assignment in the .qsf. However, it is must to provide a clock of 100-125 MHz at its input. No need to constraint it in the .sdc.
        • If you are not using transceivers, not using HMC, and not using this pin as a user-supplied configuration clock, instead want to use it as a GPIO, then you need to assign the logic port to the device CLKUSR pin location and constraint the pin in .sdc.

        We hope this information helps.


        Regards,

        Aqid