Occasional Contributor
Super Contributor
Hi Steve,
pin connection guidelines say about clkusr pin
This pin can be used as a GPIO pin only if you are not using
transceivers, not using HMC, and not using this pin as a user
supplied configuration clock.
Regards
Frank
Occasional ContributorThanks Frank -- yes that is my understanding -- my concern is by explicitly assigning the CLKUSR pin does Quartus infer that the pin is now a GPIO pin thus excluding transceiver use -- doing a project build now so will hopefully have some Quartus reporting to discuss shortly. Regards Steve
UPDATE: build complete with interesting critical warning:
Critical Warning (18326): The design pin 'clkusr' has been assigned to CLKUSR pin location 'Y15'. Quartus Prime auto-reserves the CLKUSR pin for calibration of transceivers and certain IOs. If the pin 'clkusr' will not be assigned a 100-125MHz clock, you must remove the location assignment on it. Otherwise, to remove the critical warning use the QSF assignment 'set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF'.So optimistic interpretation of the above implies that so long as clkusr pin has valid clock signal then transceivers will still calibrate correctly even when the global assignment is applied to suppress the critical warning... Digging through the Platform Designer synthesis files I found:
(*altera_attribute = "-name SDC_STATEMENT \"if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }\"" *)in "altera_a10_xcvr_reset_sequencer_211\synth\alt_sld_fab_altera_a10_xcvr_reset_sequencer_211_33t7nri.v"
