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Vigneswaran's avatar
Vigneswaran
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2 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
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Core Logic
Programmable Logic Device
Vigneswaran's avatar
Vigneswaran
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2 months ago

Hi Frank,

Can you please elaborate the below queries in sequence,  

1)Is there no headroom between ABS max and recommended max? can i select new part with VICM is 1.4 and VID is 600mV or select a part with headroom? if so how much headroom shall i implement for safer design?

2) SI5391 with VOH 1.5V falls within the acceptable limit of  TDS 1.5 I/O standard. Why is it not suitable? If so, what is the preffered chip for Agilex 7?

3) once power is provided, clock output will be present during unconfigured FPGA state, what will be the increase in VID swing with on-chip rd termination disabled? will it damage my IC?

4) I also went through the 80-0330678-D1(AGILEX 7 F-Series FPGA Development Kit), where clock is provided from ZL30733LDG1Q089 IC without any voltage shifting/dividing. How higher initial Vid due to disabled on-chip rd termination during unconfigured FPGA is handled?

5) Yes , i have got my power estimate from quartus prime based on our requirement which is "  board's power consumption". Now to find the scaling factor i need to know the "maximum power per power rail" , which value should i consider?

Appreciate your efforts,

Vigneswaran