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Vigneswaran's avatar
Vigneswaran
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4 months ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
Configuration
Core Logic
Programmable Logic Device
FvM's avatar
FvM
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4 months ago

Hi Vigneswaran,

regarding Si5391 interfacing with TDS 1.5 I/O standard, I think that VDD of 1.8 V (sub-LVDS with Vocm of 0.9 V) will better fit Agilex 5.

As for power supply requirements, they strongly depend on clock frequency and switching activity. Therefore Quartus final power estimation is performed for a synthesiszed design.

Regards
Frank