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Vigneswaran's avatar
Vigneswaran
Icon for New Member rankNew Member
5 hours ago

LVDS support on Agilex 7

HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA.  Please clear my doubt   In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
Configuration
Core Logic
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 hours ago

Hi,

I'd refer to Agilex 7 datasheet TDS I/O standard specification. With Vccio of 1.5 V, Vicm of up to 1.4 V is supported. In other words, standard LVDS peer is o.k. With Vccio of 1.2 V, a level shifting means (e.g. voltage divider) or AC coupling would be required.

Regards Frank