HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 y...
The absolute max specification of LVDS 1.5V powered IO bank is mentioned as 1.7V.
As you have stated, if VICM is 1.4 and VID is 600mV then my VOH will be 1.7V which is the absolute max rating right? is there no headroom between ABS max and recommended max?
I am planning to interface DS90LV804TSQ with Agilex, its specification mentions, VOD max as 600mV and Vos max as 1.475V which would bring my VOH to 1.775, will it not exceed Agilex specification or can i use the same part?