Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices

Hi Deva,

I read in Agilex 7 Power Management User Guide

For Agilex 7 devices, there is no power-down sequence requirement, except for Agilex 7 devices with E-Tile.

Hello, 

Basically, power down sequence is the reverse of the power up sequence. 

regards,

Farabi

Hi,

I dont have any battery backup requirement. and i have high PCB space constraint. 

is it mandatory to implement fast discharge Fets to implement power down sequence(that is reverse of Power on sequence) or can i have an uncontrolled event( with 1K Bleeder resistors on power net) such as a power supply collapse for F-Series (2x F-Tile) Devices?

Will it cause any issues that affect my chip?

Thanks in-advance,

Deva

Hi farabi,

Thanks for your valuable feedback.

So that means i can connect just a bleeder resistor to each power rail of FPGA and power down in any order(group1 may power down to 0V before Group3 on Power interruption)? 

Also, Is there any time within which all voltages must reach 0V? or can i have a large bleeder res(1K) which will discharge slowly ~1S to reach 0V.

Thanks in-advance,

Deva

Hi Farabi,

Thanks, I will implement a bleeder res which makes all the power rails ramping down not more than 100ms. 

But Kindly confirm powering down in any order is acceptable for only F tile devices i.e, group1 may power down to 0V before Group3 on Power interruption ?  (i have high PCB space constraint and will be difficult to implement fast discharge fet or to put hold up cap for sequenced power down) Is it Mandatory?

I also measured Power Down sequence in Evaluation board(agilex-pcie-dk-enpirion-revb) which has P-Tile and E-Tile, and Found there in no power down sequence being followed, which contradicts the recommendation in UG-20215. Why is it so?

Thanks in-advance,

Deva