Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices

Hi Farabi,

Thanks, I will implement a bleeder res which makes all the power rails ramping down not more than 100ms. 

But Kindly confirm powering down in any order is acceptable for only F tile devices i.e, group1 may power down to 0V before Group3 on Power interruption ?  (i have high PCB space constraint and will be difficult to implement fast discharge fet or to put hold up cap for sequenced power down) Is it Mandatory?

I also measured Power Down sequence in Evaluation board(agilex-pcie-dk-enpirion-revb) which has P-Tile and E-Tile, and Found there in no power down sequence being followed, which contradicts the recommendation in UG-20215. Why is it so?

Thanks in-advance,

Deva