Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices

Hi,

I dont have any battery backup requirement. and i have high PCB space constraint. 

is it mandatory to implement fast discharge Fets to implement power down sequence(that is reverse of Power on sequence) or can i have an uncontrolled event( with 1K Bleeder resistors on power net) such as a power supply collapse for F-Series (2x F-Tile) Devices?

Will it cause any issues that affect my chip?

Thanks in-advance,

Deva