Forum Discussion

Deva1998's avatar
Deva1998
Icon for New Contributor rankNew Contributor
2 months ago

Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices

Hi, Is there any power down sequence for  Agilex 7 F-Series (2x F-Tile) Devices? I went through Agilex™ 7 Power Management User Guide, which lists power down sequence for Agilex 7 Devices with E-Ti...
Power
Deva1998's avatar
Deva1998
Icon for New Contributor rankNew Contributor
1 month ago

Hi,

I dont have any battery backup requirement. and i have high PCB space constraint. 

is it mandatory to implement fast discharge Fets to implement power down sequence(that is reverse of Power on sequence) or can i have an uncontrolled event( with 1K Bleeder resistors on power net) such as a power supply collapse for F-Series (2x F-Tile) Devices?

Will it cause any issues that affect my chip?

Thanks in-advance,

Deva

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hello, 

     

    If you are using bleeder circuitry to speed up the power down, no issue to the FPGA. The requirements only apply to power up sequence. 

     

    regards,
    Farabi