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Deva1998's avatar
Deva1998
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26 days ago

Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices

Hi, Is there any power down sequence for  Agilex 7 F-Series (2x F-Tile) Devices? I went through Agilex™ 7 Power Management User Guide, which lists power down sequence for Agilex 7 Devices with E-Ti...
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Deva1998's avatar
Deva1998
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4 days ago

Hi farabi,

Thanks for your valuable feedback.

So that means i can connect just a bleeder resistor to each power rail of FPGA and power down in any order(group1 may power down to 0V before Group3 on Power interruption)? 

Also, Is there any time within which all voltages must reach 0V? or can i have a large bleeder res(1K) which will discharge slowly ~1S to reach 0V.

Thanks in-advance,

Deva

 

Farabi's avatar
Farabi
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1 day ago

Hello Deva, 

 

If the power down ~1sec, its too slow. Basically power down sequence is just the reverse of power up sequence. Please make all the power rails ramping down not more than 100ms. 

 

regards,

Farabi