183 Results
Why does PTP accuracy error go beyond +/- 1.5ns during dynamic reconfiguration between GTS Ethernet Hard IP and Triple-Speed Ethernet IP in Quartus® Prime Pro Edition version 26.1 and earlier?
...nd the Triple-Speed Ethernet (TSE) IP, the PTP (Precision Time Protocol) accuracy error for the GTS Ethernet Hard IP may exceed ±1.5ns in this scenario. This PTP accuracy problem does not occur with t...27Views0likes0CommentsWhy doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a n...144Views0likes0CommentsWhy does the Triple-Speed Ethernet FPGA IP report a Length Error (rx_err[1]) for undersized packets?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.3, the Triple-Speed Ethernet FPGA IP will report a Length Error (rx_err[1]) whenever an undersized packet is r...60Views0likes0CommentsWhy does the F-Tile Triple-Speed Ethernet IP Design Example fail during simulation on Windows using ModelSim* in the Quartus® Prime Pro Edition Software version 24.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, the F-Tile Triple-Speed Ethernet (TSE) IP Design Example variant - “10/100/1000 Ethernet MAC Design E...96Views0likes0CommentsWhy does the F-Tile Triple-Speed Ethernet IP with core variation 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile) drop packets?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, you may see packets dropped when the F-Tile Triple-Speed Ethernet IP is configured to 10/100/1000 Ethernet M...73Views0likes0CommentsWhy does the Agilex™ 5 Triple-Speed Ethernet FPGA IP report rx_error in RX MAC STAT at 100M and 10M speeds on the RGMII interface?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the Agilex™ 5 Triple-Speed Ethernet FPGA IP reports rx_error in RX MAC STAT at 100M and 10M speeds on the R...32Views0likes0CommentsInvalid ALT_LVDS False Path Constraints in Triple Speed Ethernet Timing Constraint File
Description The Triple Speed Ethernet SDC timing constraint file has invalid ALT_LVDS_TX megafunction false path setting that cuts a time path from 10-bits data interface to the LVDS I/O s...87Views0likes0Comments