Why fcs_client app resulted in page allocation failure and unable to proceed when executing on Agilex™ 5 SoC FPGA Devices?
Description Due to a problem with limited HPS memory resources on the Agilex™ 5 FPGA device (e.g., when deploying it with 1GB RAM or less), kernel memory allocation failures may occur, particularly when invoking crypto services operations via the HPS on a system with fragmented memory. Memory fragmentation can result from repeated crypto services operations, prolonged system uptime, or other workloads that dynamically allocate and free memory. Resolution To work around this problem, consider that the crypto services driver requires 4MB of contiguous memory for each encryption/decryption transaction in the kernel. While tuning parameters such as min_free_kbytes may help by encouraging earlier flushing of buffers or caches, they do not guarantee the reservation of contiguous memory. The Contiguous Memory Allocator (CMA) is enabled in the system, and its reserved size can be increased through kernel boot arguments to improve robustness against fragmentation-related failures. Users and system integrators are responsible for ensuring that the operating system is configured to meet the memory requirements of their expected workloads. Failure to do so may result in degraded performance, application instability, or functional failures.
Why does the Synopsys VCS* simulator produce incorrect simulation results for Agilex® 5 FPGAs?
Description The Agilex™ 5 FPGAs do not support the Synopsys VCS* two-step flow (compile and elaborate in one step and simulate in the next). You might see incorrect simulation results when simulating a multi-IP design with Synopsys VCS* simulator if you specify all IP and Quartus® simulation library source files using a single VCS command line, run_vcs. Resolution Follow these steps to use Synopsys VCS* simulator with VCS MX flow: Create design libraries using the mkdir command Compile all IP and Quartus® simulation library source files into their respective libraries using vlogan or vhdlan commands Elaborate the top-level design using the vcs command without specifying the source files compiled in Step 2 Simulate your design using the generated simv executable file The above steps are sometimes called VCS or VCS MX three-step flow (compile in one step, elaborate in the next step, and simulate in the final step). For information on which library files to be compiled, command examples, and command arguments, refer to the Platform Designer-generated VCS MX simulation setup script (/synopsis/vcsmx/vcsmx_setup. sh). If you were previously using the Platform Designer-generated VCS simulation setup script (/synopsys/vcs/vcs_setup.sh), switch to using the Platform Designer-generated VCS MX simulation setup script (/synopsys/vcsmx/vcsmx_setup.sh). Refer to Quartus® Prime Pro Edition User Guide: Third-party Simulation for more guidelines on incorporating the generated Synopsys VCS MX simulation scripts into a top-level project simulation setup script. Agilex® 5 FPGA no longer supports the VCS 2-step flow; only the VCS 3-step flow is supported.Why do several IP design examples fail on the Agilex® 7 FPGA Series Transceiver SoC Development Kit?
Description The following IP Cores generate example designs for the Agilex® 7 FPGA Series Transceiver SoC Development Kit with incorrect VID settings. 1) Serial Lite IV IP 2) Interlaken (2nd Generation) IP 3) Triple-Speed Ethernet IP 4) E-Tile Dynamic Reconfiguration IP 5) E-Tile Hard IP for Ethernet and CPRI PHY IP 6) JESD204B IP 7) JESD204C IP 8) Ethernet Subsystem IP Resolution The correct VID settings can be found in section 6.1, Add SmartVID settings in the Quartus® Prime QSF file of the Agilex® F-Series Transceiver-SoC Development Kit User Guide. Update the design examples with the correct VID settings as shown below: set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ" set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42 set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00 set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00 set_global_assignment -name USE_PWRMGT_SCL SDM_IO0 set_global_assignment -name USE_PWRMGT_SDA SDM_IO12 set_global_assignment -name USE_CONF_DONE SDM_IO16 set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER" set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT" set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13" set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why are the inputs and/or outputs from my Agilex® 7 FPGA device inverted?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and later, signals from the banks listed below may be inverted. This only affects IO Cells where any of the IO registers are enabled. Device GPIO Bank AGIB041, AGID041 3C and 3D AGFB006, AGFB008 3C and 3D AGFB012, AGFB014 3C and 3D AGFB019, AGFB023, AGFD019, AGFD023 AGIB019, AGIB023, AGID019, AGID023 3A and 3B AGFB022, AGFB027 AGIB022, AGIB027 3C and 3D Resolution To work around this problem, disable register packing for these GPIO banks. This problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1.Why does the Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Quartus Prime Pro Edition Software version 19.4 and later.Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller?
Description Due to a problem in the Intel® Stratix® 10 MX HBM2 controller when using the Intel Quartus® Prime Pro Edition software versions 20.4 or earlier, you may see that the AXI master returns a different value for the read address ID axi_0_0_rid signal if the read burst length axi_0_0_arlen signal is greater than 2. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 20.4 or earlier, Download hbm_burst_rid_fix.zip file and replace the following encrypted files from the existing ones. ./sim_mentor/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_191/sim/mentor/ ./syn_quartus/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_19 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.Why does my Arria 10 SoC industrial grade device fail to boot at low temperature?
Description Certain Hard Processor System (HPS) PLL clock output frequencies require a specific programming setup sequence to ramp the PLL frequency gradually in Arria 10 SoC industrial grade devices at -40degreesC, otherwise the HPS may fail to boot. Resolution To workaround this issue in SoC EDS software version 16.0, download the patch below and follow the instructions in the readme. Download the SoC EDS software version 16.0 Patch 002soc for Linux(.run) Download the Readme for SoC EDS software version 16.0 Patch 002soc for Linux(.txt) The corresponding patch for socfpga UEFI is available in the rel_socfpga_arria10_soceds_16.0 tag of the socfpga_udk2015 branch from the github repository: https://github.com/altera-opensource/uefi-socfpga. This problem is scheduled to be fixed in a future version of the SoC EDS software.Is there a known issue for the Intel® Stratix® 10 devices when SEU detection is enabled?
Description Users may encounter the Intel® Stratix® 10 devices not functioning as expected when reconfiguring the FPGA by toggling the nCONFIG low OR, via JTAG OR, when using Partial Reconfiguration (PR). This issue may only occur if the design enables SEU detection on all configuration modes: i.e. ASx4, AVSTx8/x16/x32, JTAG Once the issue is observed: In the case of reconfiguration, you must power cycle the FPGA to recover. In the case of PR, you can reconfigure the base design or power cycle the FPGA to recover. Resolution If SEU detection is not required, disable SEU detection If SEU detection is required, download and install the patch from the corresponding link below. Then, regenerate the bitstream (RBF/JIC/RPD/POF) with the existing SOF. Recompilation is NOT required. Patch for Intel® Quartus® Pro version 20.1: Download the version 20.1 patch 0.46 for Windows (.exe) Download the version 20.1 patch 0.46 for Linux (.run) Patch for Intel® Quartus® Pro version 20.2: Download the version 20.2 patch 0.47 for Windows (.exe) Download the version 20.2 patch 0.47 for Linux (.run) Patch for Intel® Quartus® Pro version 20.3: Download the version 20.3 patch 0.08 for Windows (.exe) Download the version 20.3 patch 0.08 for Linux (.run) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4.Why does my Intel® Stratix® 10 design fail to boot / read from QSPI when using the Intel® Quartus® Prime Pro Software version 21.1 or 21.2 to create full flash images such as .JIC / .RPD files?
Description Due to a problem in the Quartus® Programming File Generator in the Intel® Quartus® Prime Pro Software version 21.1, and 21.2, block partitions containing raw data files (.hex, .bin, .puf or .wkey) may be incorrectly re-sized in full flash images (.JIC / .RPD files). This problem may result in run-time boot failures, data corruption, or QSPI corruption when Intel® Stratix® 10 Hard Processor System Remote System Update (RSU) flows are used to update flash content. Resolution Patch 0.14 for the Intel® Quartus® Prime Pro Software version 21.2 is available to fix this problem. 1. Download and install the patch from the relevant link below quartus-21.2-0.14-linux.run quartus-21.2-0.14-windows.exe quartus-21.2-0.14-readme.txt 2. Re-Create the Flash image clean, re-entering all partition data and sizing. 3. Re-program your QSPI flash using the new .JIC / .rpd file This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Related KDB : Is there any problem when raw data file is added in a programming file using Block Address Mode?When using the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express Avalon-ST, why is the host system unable to detect the PCIe link or fail to boot up from BIOS?
Description Due to a problem with the Intel® Quartus® Prime Pro Edition software version 19.3, you may encounter the above problem, this is due to an incorrect implementation of the pld_clk_inuse signal of the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI* Express. Resolution A patch is available to fix this problem. Download and install patch 0.26 for Intel® Quartus® Prime Pro Edition software version 19.3. Download patch 0.26 for Windows* (quartus-19.3-0.26-windows.exe) Download patch 0.26 for Linux* (quartus-19.3-0.26-linux.run) Download the Readme for patch 0.26 (quartus-19.3-0.26-readme.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.4.