Why do I see the HPS on Intel Agilex® SoC devices fail to boot, or observe some unexpected functional failures at run time?
Description Due to a problem in the device manager firmware, you might fail to read/write certain RAMs on some Intel Agilex® SoC devices. Impacted HPS RAMs include L2 cache, OCRAM, CCU, USB, CoreSight, and EMAC. You might observe the following HPS boot failures: HPS hangs at dcache memory write and read after executing the dcache_enable function in FSBL UART printout stops after “DDR: 8192 MiB” UART printout stops after “Loading Environment from MMC… ***” UART printout stops after “Verifying Hash Integrity … crc32” Various unexpected functional failures depending on the faulty RAM location Resolution To resolve this problem, update to the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software v21.2, 21.3, 21.4, 22.1, and 22.2. The latest device manager firmware is available from the following link: What is the latest device firmware for Intel Agilex® and Intel® Stratix® 10 devices? This problem is fixed beginning with version 22.4 of the Intel® Quartus® Prime Pro Edition software.Warning (16817): Verilog HDL warning at altera_xcvr_*_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_*_reconfig_parameters package
Description If your design contains multiple JESD204B IPs with different configurations, you may see the following warning in Intel® Quartus® Prime Pro software version 15.1 or later during Analysis and Synthesis stage. When targetting Intel Stratix® 10 devices: Warning (16817): Verilog HDL warning at altera_xcvr_rcfg_10_reconfig_parameters.sv: overwriting previous definition of module altera_xcvr_rcfg_10_reconfig_parameters When targetting Intel Arria® 10 or Intel Cyclone® 10 GX devices: Warning (16817): Verilog HDL warning at altera_xcvr_native_a10_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_native_a10_reconfig_parameters package If your design does not rely on the *_reconfig_parameters.sv package files for performing transceiver reconfiguration, it is safe to ignore the warning. Resolution If your design must include the reconfiguration packages, ensure the uniqueness of each of the packages by renaming the packages. For example, a design that contains two simplex RX interfaces with different data rates, assign a unique name by changing the package module from: package altera_xcvr_native_a10_reconfig_parameters; To: package altera_xcvr_native_a10_reconfig_parameters_inst1; In the first instance of RX, and changing to another unique name: package altera_xcvr_native_a10_reconfig_parameters_inst2; In the second instance of RX. Then, import those packages into your design per your design requirements.Why does the Intel® FPGA Download Cables drivers installation fail on Windows* operating system?
Description Due to the expiration of the digital signature certificate of the Intel® FPGA Download Cable I (formerly referred to as USB Blaster I download cable) and the Intel® FPGA Download Cable II (formerly referred to as USB Blaster II download cable) drivers for Windows* operating system, the installation process of the drivers may fail. Follow the next steps to verify if the digital signature certificate of your driver has expired: Go to '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Right-click on 'usbblasterii.cat' and select 'Properties, then select the 'Digital Signatures' tab Select the 'IFDLII Production Key1' signature from the 'Signature List' and click 'Details' Click on 'View Certificate' If the driver has expired, you will see the 'This certificate has expired or is not yet valid' message Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Software. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 21.1. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Programmer and Tools or Patch 0.02stdp for the Intel® Quartus® Prime Standard Edition Programmer and Tools from the appropriate link below. Download Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i for Windows (.exe) Download the Readme for Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i (.txt) Download Intel® Quartus® Prime Standard Edition Software version 21.1patch 0.02stdp for Windows (.exe) Download the Readme for Intel® Quartus® Prime Standard Edition Software version 21.1 patch 0.02stdp (.txt) After installing patch 0.02i or patch 0.02stdp for Windows, follow the next steps to update the driver on the operating system: Connect your Intel FPGA download cable or Intel FPGA download cable II Open Device Manager window of Windows* OS Choose Windows Settings from Start menu > Type “Device Manager” into the search area > Choose Device Manager Find Altera USB-Blaster II under JTAG cables or Altera USB-Blaster under Universal Serial Bus controllers Find USB-Blaster or USB-Blaster II under Other devices Choose Altera USB-Blaster or Altera USB-Blaster II Right-click and choose Update driver from the context menu Choose Browse my computer for driver software on the Update Drivers window Enter the following path for the driver and enable; include subfolders - <Intel Quartus Prime software install directory>\quartus\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\quartus\drivers Click Next This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.Compiling a Design from the Command-Line in the Windows Version of the Quartus Prime Pro Edition Software Might Result in Blank Messages in the Report Panel
Description For the Windows version of the Quartus ® Prime Pro Edition software, compiling a design from the command-line might result in blank messages in the Report panel. For example, the .syn.rpt file might be blank. Resolution Compile your deisgn using the Quartus Prime Pro Edition software GUI on Windows.Is there a known issue for the Intel® Stratix® 10 devices when SEU detection is enabled?
Description Users may encounter the Intel® Stratix® 10 devices not functioning as expected when reconfiguring the FPGA by toggling the nCONFIG low OR, via JTAG OR, when using Partial Reconfiguration (PR). This issue may only occur if the design enables SEU detection on all configuration modes: i.e. ASx4, AVSTx8/x16/x32, JTAG Once the issue is observed: In the case of reconfiguration, you must power cycle the FPGA to recover. In the case of PR, you can reconfigure the base design or power cycle the FPGA to recover. Resolution If SEU detection is not required, disable SEU detection If SEU detection is required, download and install the patch from the corresponding link below. Then, regenerate the bitstream (RBF/JIC/RPD/POF) with the existing SOF. Recompilation is NOT required. Patch for Intel® Quartus® Pro version 20.1: Download the version 20.1 patch 0.46 for Windows (.exe) Download the version 20.1 patch 0.46 for Linux (.run) Patch for Intel® Quartus® Pro version 20.2: Download the version 20.2 patch 0.47 for Windows (.exe) Download the version 20.2 patch 0.47 for Linux (.run) Patch for Intel® Quartus® Pro version 20.3: Download the version 20.3 patch 0.08 for Windows (.exe) Download the version 20.3 patch 0.08 for Linux (.run) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4.Using the Altera SDK for OpenCL Version 16.0.1 to Compile an OpenCL Design that Targets a 16.0 Version of the Arria 10 Reference or Custom Platform Results in a Fatal Error
Description If you use the Altera ® SDK for OpenCL ™ (AOCL) version 16.0.1 to compile an OpenCL design that targets a 16.0 version of the Arria 10 Reference or Custom Platform (for example, Arria ® 10 GX FPGA Development Kit Reference Platform), the Altera Offline Compiler will encounter a fatal error with the following error message: Error: Compiler Error, not able to generate hardware In addition, the <kernel_name>/quartus_sh_compile.log file includes the following error messages: Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design. Error (15744): In atom \'board_inst|pcie|altpcie_a10_hip_pipen1b|wys\' Error (15744): The settings must match one or more of these conditions: Error (15744): ( g3_ltssm_rec_dbg == TRUE ) OR ( sim_mode == ENABLE ) OR ( sup_mode == ENGINEERING_MODE ) Error (15744): But the following assignments violate the above conditions: Error (15744): g3_ltssm_rec_dbg = FALSE Error (15744): sim_mode = DISABLE Error (15744): sup_mode = USER_MODE Error (18590): The imported netlist contains settings that are not supported by the current version of the software. Import using the --timing_analysis_mode option, which ignores the errors and allows Timing Analysis to be run. Error: design::import_design -file base.qdb -overwrite failed! Resolution Use a version of the AOCL that matches the version of your Arria 10 Reference or Custom Platform. If you wish to use AOCL version 16.0.1, contact your board vendor to acquire the 16.0.1 version of the Arria 10 Custom Platform (if available).Why is the IEEE 1588 PTP delay/offset measurement is inconsistent on 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP ?
Description Due to a problem with the Intel® Quartus® Prime Software version 21.2 and earlier, the gmii16b_rx_latency of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP output signal may potentially drift between 0 (min) and 0x3FFFFF (max) when Tx clock (tx_serial_clk), Rx clock (rx_cdr_refclk), link partner Tx data channel reference clock and recommended 80MHz latency_measure_clk of the IP core share a common clock source. As a result, the generated Rx timestamps are not accurate, and the measured delay/offset is much larger than expected in IEEE 1588 applications. However, the gmii16b_tx_latency signal is not impacted by this problem. This problem only impacts 1G and 2.5G IEEE 1588 operations. 5G and 10G IEEE 1588 operations are not affected. Resolution Modify IP core latency_measure_clk clock frequency from 80MHz to either 79.98MHz or 80.02MHz to avoid this problem. This modification can also be applied to the 80MHz sampling clock frequency of TOD Synchronizer Intel® FPGA IP and will not affect PTP timestamping accuracy. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why does the HDMI 2.1 Intel® FPGA Source IP output the wrong VSYNC and HSYNC polarity?
Description Due to a problem starting from the Intel® Quartus® Prime Pro Edition Software version 19.4, you may see the HDMI 2.1 Intel® FPGA Source IP in TMDS mode output incorrect VSYNC and HSYNC polarity. This problem only impacts the HDMI 2.1 Intel® FPGA Source IP in TMDS mode. This problem does not impact HDMI 2.1 Intel® FPGA Source IP in FRL mode or HDMI 2.0 Intel® FPGA Source IP Note: HDMI 2.1 is enabled when setting Support FRL = 1 while HDMI 2.0 is enabled when setting Support FRL = 0. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why are TLPs being lost when using the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express may fail to capture the pX_tx_st_eop_i signal assertion from the application logic at the Avalon® Streaming TX interface. As a result, the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express will drop the Avalon® Streaming packet and will not generate the corresponding Transaction Layer Packet (TLP). The following Avalon® Streaming packet delivered to the Avalon® Streaming TX interface may not be affected by this problem. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v21.3.Why is there a hold slack difference when performing timing analysis using the -force_dat option in the Timing Analyzer?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1 and 20.2, you may see a hold slack difference in Intel® Stratix® 10 designs when using any of the High Performance or Superior Performance compilation modes. This is due to a missing timing arc that is introduced during optimization work in the compiler. Resolution If you are still in the design phase of your project, and are using Intel® Quartus® Prime Pro Edition Software version 20.1 or 20.2, but cannot move to the latest version, download and install the patch from the link below. Recompile your design with the patch installed. If you are targeting Intel® Quartus® Prime Pro Edition Software version 20.1 or 20.2, and your project is finalized and in the production phase, but cannot move to the latest version, follow-through step (1) to (3) for impact assessment and necessary actions each individual compilation: 1) Download this script to your project folder, missing_hold_timing_arc.tcl 2) Execute this command from the command line: quartus_sta –t missing_hold_timing_arc.tcl –proj <project name> [-rev <revision name> ] 3) The script will return 1 of the following 4 outputs. Follow the corresponding instructions: i) Design needs to be recompiled. Install patch 0.30 for the Intel Quartus Prime Pro Edition Software v20.1 and recompile. Download patch 0.30 for Intel Quartus Prime Pro Edition Software v20.1 for Windows (.exe) Download patch 0.30 for Intel Quartus Prime Pro Edition Software v20.1 for Linux (.run) Download the readme for patch 0.30 for Intel Quartus Prime Pro Edition Software v20.1 (.txt) ii) Design needs to be recompiled. Install patch 0.19 for the Intel Quartus Prime Pro Edition Software v20.2 and recompile. Download patch 0.19 for Intel Quartus Prime Pro Edition Software v20.2 for Windows (.exe) Download patch 0.19 for Intel Quartus Prime Pro Edition Software v20.2 for Linux (.run) Download the readme for patch 0.19 for Intel Quartus Prime Pro Edition Software v20.2 (.txt) iii) No timing violations. Recompilation for this seed is not necessary. This seed is not affected by this problem but if the design is recompiled without the patch then the script must be rerun. iv) This version of Intel Quartus Prime Pro Edition Software does not need to be patched. This message will only appear in the Intel® Quartus® Prime Pro Edition Software versions other than 20.1 and 20.2. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 20.3.
