Why does the Intel® FPGA Download Cables drivers installation fail on Windows* operating system?
Description Due to the expiration of the digital signature certificate of the Intel® FPGA Download Cable I (formerly referred to as USB Blaster I download cable) and the Intel® FPGA Download Cable II (formerly referred to as USB Blaster II download cable) drivers for Windows* operating system, the installation process of the drivers may fail. Follow the next steps to verify if the digital signature certificate of your driver has expired: Go to '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Right-click on 'usbblasterii.cat' and select 'Properties, then select the 'Digital Signatures' tab Select the 'IFDLII Production Key1' signature from the 'Signature List' and click 'Details' Click on 'View Certificate' If the driver has expired, you will see the 'This certificate has expired or is not yet valid' message Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Software. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 21.1. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Programmer and Tools or Patch 0.02stdp for the Intel® Quartus® Prime Standard Edition Programmer and Tools from the appropriate link below. Download Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i for Windows (.exe) Download the Readme for Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i (.txt) Download Intel® Quartus® Prime Standard Edition Software version 21.1patch 0.02stdp for Windows (.exe) Download the Readme for Intel® Quartus® Prime Standard Edition Software version 21.1 patch 0.02stdp (.txt) After installing patch 0.02i or patch 0.02stdp for Windows, follow the next steps to update the driver on the operating system: Connect your Intel FPGA download cable or Intel FPGA download cable II Open Device Manager window of Windows* OS Choose Windows Settings from Start menu > Type “Device Manager” into the search area > Choose Device Manager Find Altera USB-Blaster II under JTAG cables or Altera USB-Blaster under Universal Serial Bus controllers Find USB-Blaster or USB-Blaster II under Other devices Choose Altera USB-Blaster or Altera USB-Blaster II Right-click and choose Update driver from the context menu Choose Browse my computer for driver software on the Update Drivers window Enter the following path for the driver and enable; include subfolders - <Intel Quartus Prime software install directory>\quartus\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\quartus\drivers Click Next This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.Is the Nios® II Software Build Tools (SBT) for Eclipse included in the full installation of the Intel® Quartus® Prime Pro Edition Software starting from version 19.1?
Description No, the Nios® II SBT for Eclipse is not included starting from Intel® Quartus® Prime Pro and Standard Edition Software version 19.1 onwards. Resolution To install the Nios® II SBT for Eclipse, follow the steps below: 1. Download CDT 8.8.1 which is Eclipse C/C IDE for Mars.2 CDT 8.8.1 for Windows CDT 8.8.1 for Linux Note: Try the mirror links if the main source link doesn't work. 2. Extract the downloaded file into <Intel Quartus installation directory>/nios2eds/bin. You should see the <Intel Quartus installation directory>/nios2eds/bin/eclipse folder after extraction is done. 3. Rename the <Intel Quartus installation directory>/nios2eds/bin/eclipse folder to <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2 4. Extract the <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2_plugins.zip (or tar.gz for Linux) to <Intel Quartus installation directory>/nios2eds/bin. The extraction will override files in <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2. 5. Verify the extraction is done correctly by making sure you see the <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2/plugin_customization.ini file 6. You can now launch Nios II SBT for Eclipse via eclipse-nios2.exe The instructions are included in the <Intel Quartus installation directory>/nios2eds/bin/README. This information will be included in the future release version of Intel® FPGA Software Installation and Licensing User Guide.Why does the Quartus® Prime Pro Edition Programmer program pof file to DK-DEV-AGI027RBES unsuccessfully when following the R-Tile FPGA IP for Compute Express Link* (CXL*) Design Example User Guide?
Description Due to a problem in the R-Tile FPGA IP for Compute Express Link* (CXL*) Design Example User Guide, version 1.10.0, you might observe pof programming failure on DK-DEV-AGI027RBES when following the chapter "C. Programming the Agilex™ 7 FPGA Development Kit with an External USB Blaster II", the description for the programming steps of DK-DEV-AGI027R1BES and DK-DEV-AGI027RBES is not separate and clear enough. Resolution To work around this problem, refer to the following instructions: 1. The programming steps for DK-DEV-AGI027R1BES: Connect an external USB blaster II into the J10- External JTAG header. Set the switch SW5.3 to ON (for the first time). Open the Quartus® Prime Pro Edition Software programmer tool. Click the Hardware Setup, and select USB Blaster II. Set the Hardware Frequency to 16000000Hz and uncheck the Auto-adjust frequency at chain scanning box. Click Close. Click Auto Detect and select MAX® 10 device, click OK. Right-click on the MAX® 10 device, and select Edit -> Change File. Select the MAX® 10 SOF file image: max10_bmc_avstx8_test.sof and click Open. Check the Program/Configure box and click Start to start the programming operation. When the operation is 100% successfully completed, click Auto Detect. Click Yes on pop-up windows. Right click on the QSPI_2Gb device, select Edit -> Change File. Select the POF file image: file.pof and click Open. Check Program/Configure box of QSPI_2Gb, P1, OPTION_BITS and click Start to start the programming operation. When the operation is 100% successfully completed, close the programmer window, shut down the platform (Pressing the on-off button on your server instead of typing “poweroff” in command window), set SW5.3 to OFF, disconnect USB Blaster II and boot the platform again. Type “lspci -vt ” in the command window, 0ddb device should be found. 2. The programming steps for DK-DEV-AGI027RBES: Plug in the USB cable to the USB port J8 (when using J10, DIPSWITCH SW5.3 (DK-DEV-AGI027RES and DK-DEV-AGI027R1BES) and SW8.3 (DK-DEV-AGI027RB and DK-DEV-AGI027-RA) should be off). Set the DIPSWITCH SW2 to [on:off:off:X] (the 4th bit is don't care). You can follow this combination which has been verified on the hardware: SW1=ON/Off/Off/Off; SW2=ON/Off/Off/Off; SW3=Off/ON/ON/Off; SW4=Off/Off/ON/Off; SW5=Off/Off/Off/Off; SW8=Off/Off/Off/Off Open the Quartus® Prime Pro Edition Software programmer tool. Click the Hardware Setup, and select USB Blaster II. Set the Hardware Frequency to 16000000Hz and uncheck the Auto-adjust frequency at chain scanning box. Click Close. Click Auto Detect to scan the JTAG devices. If the JTAG chain can not be detected, try setting SW4:3 to OFF. If a device called 1_BIT_TAP appears between AGIB027R29AR0 and VTAP10, ignore it and continue to the next step. Right click the VTAP10 device, Edit > Change Device, change it to MAX 10 > 10M50DAF256. Right click the 10M50DAF256 device, Edit > Attach Flash Device, select Quad SPI Flash Memory QSPI_2Gb. In the Programmer page, click QSPI_2Gb > Change File to select the .pof file. Start the Programmer. When the operation is 100% successfully completed, close the programmer window, and shut down the platform (Pressing the on-off button on your server instead of typing “poweroff” in the command window), if SW4:3 was OFF before, set it to ON, disconnect USB Blaster II and boot the platform again. Type “lspci -vt ” in the command window, 0ddb device should be found.Why does the BAR offset of the MSI-X Table and PBA for Intel® Stratix® 10 PCI Express* Hard IP fail to take effect?
Description Due to the issue of Intel® Quartus® Prime Pro software, the MSI-X Table BAR offset and PBA specified in the GUI for Intel® Stratix® 10 PCI Express* Hard IP, fail to take effect. This can be seen by using the “lspci” command on Linux OS. Hence the MSI-X functionality will fail to operate correctly due to the address of MSI-X Table overlapping the PBA. This issue impacts the following IP cores: Intel® Stratix® 10 Avalon®-MM interface for PCI Express* Intel® Stratix® 10 Avalon®-ST interface for PCI Express* Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express*. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.3.Why are Non-Fatal PCIe* errors logged in Advanced Error Reporting (AER) when using the Intel® FPGA P-Tile/H-Tile , Avalon® Streaming and Avalon® Memory Mapped IP for PCI Express*?
Description The P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* implements optional Alternative Routing-ID Interpretation (ARI) capability when Multi-function or Single Root I/O Virtualization (SR-IOV) features are enabled. ARI capability includes a field called next function number to help the host BIOS to perform the enumeration process. When ARI is enabled and the number of Physical Functions (PFs) is less than 8 for P-Tile, or 4 for H-tile, the next function number incorrectly shows a value of PF 1. As a result, the following error status bits in the endpoint may get set if AER is enabled, as the Root Port issues a configuration request to the non-existing PF pointed to by the incorrect next function number: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only set if Advisory Non-Fatal Error Mask bit is set to ‘0’ (Correctable Error Mask Register) An ERR_COR message will be sent to the Root Port if AER is enabled by setting the following bits below: Advisory Non-Fatal Error Mask is set to '0' (Correctable Error Mask Register) Correctable Error Reporting Enable is set to '1' (Device Control Register) Unsupported Request Reporting Enable is set to '1' (Device Control Register) In the Root Port, the following bit will be set if Completion with Unsupported Request status is received Received Master Abort (Secondary Status Register) Also, in the Root Port, the following bit will be set if ERR_COR is received, and AER is enabled ERR_COR Received (Root Error Status Register) Resolution For the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* and For the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express*, software can ignore the detected errors each time enumeration is done. If the following error status bits are set in the endpoint after enumeration, then it is safe for the software to ignore them: Correctable Error Detected (Device Status Register) Unsupported Request Detect (Device Status Register) Advisory Non-Fatal Error Status (Correctable Error Status Register) Unsupported Request Error Status (Uncorrectable Error Status Register) Only if Advisory Non-Fatal Error Mask bit (Correctable Error Mask Register) is set to ‘0’ For simplicity, the workaround can be done in the following order Upon enumeration complete, clear the error registers below (all bits irrespectively) for all PCIe Endpoint Functions Device Status Register Correctable Error Status Register Uncorrectable Error Status Register Clear the error registers below (all bits irrespectively) for the PCIe Root Port related to the PCIe Endpoint Functions above Secondary Status Register Root Error Status Register Repeat step 1 and step 2 for each PCI enumeration process. If runtime polling for errors is being performed, bits 'Correctable Error Detected', 'Unsupported Request Detect', 'Advisory Non-Fatal Error Status' and 'Unsupported Request Error Status' can be checked by the polling software to differentiate this issue from other reliability errors. If only those 4 bits are set, we can assume the errors on the endpoints are related to the P-Tile/H-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* or the P-Tile/H-Tile Avalon® Memory Mapped Intel® FPGA IP for PCI Express* issue and it is appropriate to proceed to clear the error status bits listed in step 1 and step 2 above. For P-Tile, user logic can use the Configuration Intercept Interface (CII) to correctly advertise the ARI next function number when a Configuration Read is issued by the Root Port.SEVERE: An error occurred while running script "::emif_cal_dbg::odt_cal::run_odt_cal_callback
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.2, you may see a similar error to the one shown below when a calibration failure occurs in the Intel Stratix® 10 EMIF Unified Calibration Debug Toolkit or the Intel Agilex® 3 FPGA EMIF Debug Toolkit. SEVERE: An error occurred while running script"::emif_cal_dbg::odt_cal::run_odt_cal_callback ": ed_synth_inst: key "65542" not known in dictionary while executing "dict get $dictionary $key" (procedure "::emif_cal_dbg::util::family_expert::get_dict_elem" line 3) invoked from within "::emif_cal_dbg::util::family_expert::get_dict_elem cal_stage [expr $val]" Resolution This example error message displays an error code “65542” when a calibration failure occurs and is not reported by the EMIF Toolkit. For the Intel® Stratix® 10 EMIF Unified Calibration Debug Toolkit, below is a list of the calibration stages and associated error codes that are not reported. Calibration Stage Error Code WRITE_LEVEL_EDGE 65541 WRITE_LEVEL_CLOCK 131077 WRITE_DESKEW_DM_CENTER 65542 MARGINING_DQ 65547 MARGINING_DM 131083 For the Intel Agilex® 3 FPGA EMIF Debug Toolkit, below is a list of the calibration stages and associated error codes that are not reported. Calibration Stage Error Code WRITE_LEVEL_EDGE: 65541 WRITE_LEVEL_CLOCK: 131077 WRITE_DESKEW_DM_CENTER: 65542 READ_DESKEW_DBI_CENTER: 65540Installing an unsigned driver might cause an error in the Altera SDK for OpenCL running on Windows 8.1
Description If you run the Altera SDK for OpenCL version 15.1 on Windows 8.1 and you install an unsigned driver, you might encounter the following error messages: difx_install_preinstall_inf: err e000024b, last event 0, last error 0. UNKNOWN difx_install_preinstall_inf: err e000022f, last event 0, last error 0. UNKNOWN Resolution Prior to installing an unsigned driver, disable driver signature enforcement by performing the following steps: On the Windows login screen or under the Charms bar, open the power options menu. Hold the Shift key while you click Restart from the power options menu. After your computer reboots, select the Troubleshoot option. Select Advanced Options. Select Startup Settings. When prompted, click Restart to reboot your computer. When the Startup Settings menu appears, press the F7 key to choose the Disable driver signature enforcement option. After your computer restarts, you can install unsigned drivers.What is the latest device firmware for the Agilex® FPGA and Stratix®10 FPGAs?
Description Altera® recommends using the latest version of the Quartus® Prime Pro Edition Software and the latest available device firmware. Please also see the following user guides: Updating the SDM Firmware in the Agilex® 7 FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution The latest device firmware available for the Quartus® Prime Pro Edition Software can be downloaded from the following links: Quartus Prime Pro Edition Software version 25.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.3? Quartus Prime Pro Edition Software version 25.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1? Quartus Prime Pro Edition Software version 24.3.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3.1? Quartus Prime Pro Edition Software version 24.3 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.3? Quartus Prime Pro Edition Software version 24.2 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.2? Quartus Prime Pro Edition Software version 24.1 What is the latest device firmware for the Quartus® Prime Pro Edition Software version 24.1? Quartus Prime Pro Edition Software version 23.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.4? Quartus Prime Pro Edition Software version 23.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.3? Quartus Prime Pro Edition Software version 23.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.2? Quartus Prime Pro Edition Software version 23.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 23.1? Quartus Prime Pro Edition Software version 22.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.4? Quartus Prime Pro Edition Software version 22.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.3? Quartus Prime Pro Edition Software version 22.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.2? Quartus Prime Pro Edition Software version 22.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 22.1? Quartus Prime Pro Edition Software version 21.4 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.4? Quartus Prime Pro Edition Software version 21.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.3? Quartus Prime Pro Edition Software version 21.2 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.2? Quartus Prime Pro Edition Software version 21.1 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 21.1? Quartus Prime Pro Edition Software version 20.3 What is the latest device firmware available for the Quartus® Prime Pro Edition Software version 20.3?xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/ct1_hssi_atoms_ncrypt.sv.
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3 installation package for Linux operating system (OS), the following errors may be reported during simulation when using the Cadence Xcelium simulator. xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/ct1_hssi_atoms_ncrypt.sv. xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/cr3v0_serdes_models_ncrypt.sv. xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/ct1_hip_atoms_ncrypt.sv. xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/ctp_hssi_atoms_ncrypt.sv. xrun: *E,FILEMIS: Cannot find the provided file /quartus_pro/20.3/quartus/eda/sim_lib/cadence/cta_hssi_atoms_ncrypt.sv. Resolution Download the following patch to install the missing simulation libraries for the Intel® Quartus® Prime Pro Edition Software v20.3 in Linux OS: Intel® Quartus® Prime Pro Edition software version 20.3 Patch 0.14 Linux (.run) Readme for Intel® Quartus® Prime Pro Edition software version 20.3 Patch 0.14 (.txt) This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software v20.4.Intel® Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
Description The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC. When this happens, no error is reported by the Intel® Arria® 10 FPGA. This is an expected behaviour. Resolution To work around this problem, disable the Data Link Feature Exchange in PCIe 4.0 system [Base spec 4.0 chapter 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware. This problem will not be fixed in a future release of the Intel® Quartus® Prime Software.
