Why does the Intel® FPGA Download Cables drivers installation fail on Windows* operating system?
Description Due to the expiration of the digital signature certificate of the Intel® FPGA Download Cable I (formerly referred to as USB Blaster I download cable) and the Intel® FPGA Download Cable II (formerly referred to as USB Blaster II download cable) drivers for Windows* operating system, the installation process of the drivers may fail. Follow the next steps to verify if the digital signature certificate of your driver has expired: Go to '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Right-click on 'usbblasterii.cat' and select 'Properties, then select the 'Digital Signatures' tab Select the 'IFDLII Production Key1' signature from the 'Signature List' and click 'Details' Click on 'View Certificate' If the driver has expired, you will see the 'This certificate has expired or is not yet valid' message Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Software. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 21.1. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Programmer and Tools or Patch 0.02stdp for the Intel® Quartus® Prime Standard Edition Programmer and Tools from the appropriate link below. Download Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i for Windows (.exe) Download the Readme for Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i (.txt) Download Intel® Quartus® Prime Standard Edition Software version 21.1patch 0.02stdp for Windows (.exe) Download the Readme for Intel® Quartus® Prime Standard Edition Software version 21.1 patch 0.02stdp (.txt) After installing patch 0.02i or patch 0.02stdp for Windows, follow the next steps to update the driver on the operating system: Connect your Intel FPGA download cable or Intel FPGA download cable II Open Device Manager window of Windows* OS Choose Windows Settings from Start menu > Type “Device Manager” into the search area > Choose Device Manager Find Altera USB-Blaster II under JTAG cables or Altera USB-Blaster under Universal Serial Bus controllers Find USB-Blaster or USB-Blaster II under Other devices Choose Altera USB-Blaster or Altera USB-Blaster II Right-click and choose Update driver from the context menu Choose Browse my computer for driver software on the Update Drivers window Enter the following path for the driver and enable; include subfolders - <Intel Quartus Prime software install directory>\quartus\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\quartus\drivers Click Next This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.Why do I see the HPS on Intel Agilex® SoC devices fail to boot, or observe some unexpected functional failures at run time?
Description Due to a problem in the device manager firmware, you might fail to read/write certain RAMs on some Intel Agilex® SoC devices. Impacted HPS RAMs include L2 cache, OCRAM, CCU, USB, CoreSight, and EMAC. You might observe the following HPS boot failures: HPS hangs at dcache memory write and read after executing the dcache_enable function in FSBL UART printout stops after “DDR: 8192 MiB” UART printout stops after “Loading Environment from MMC… ***” UART printout stops after “Verifying Hash Integrity … crc32” Various unexpected functional failures depending on the faulty RAM location Resolution To resolve this problem, update to the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software v21.2, 21.3, 21.4, 22.1, and 22.2. The latest device manager firmware is available from the following link: What is the latest device firmware for Intel Agilex® and Intel® Stratix® 10 devices? This problem is fixed beginning with version 22.4 of the Intel® Quartus® Prime Pro Edition software.Is the Nios® II Software Build Tools (SBT) for Eclipse included in the full installation of the Intel® Quartus® Prime Pro Edition Software starting from version 19.1?
Description No, the Nios® II SBT for Eclipse is not included starting from Intel® Quartus® Prime Pro and Standard Edition Software version 19.1 onwards. Resolution To install the Nios® II SBT for Eclipse, follow the steps below: 1. Download CDT 8.8.1 which is Eclipse C/C IDE for Mars.2 CDT 8.8.1 for Windows CDT 8.8.1 for Linux Note: Try the mirror links if the main source link doesn't work. 2. Extract the downloaded file into <Intel Quartus installation directory>/nios2eds/bin. You should see the <Intel Quartus installation directory>/nios2eds/bin/eclipse folder after extraction is done. 3. Rename the <Intel Quartus installation directory>/nios2eds/bin/eclipse folder to <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2 4. Extract the <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2_plugins.zip (or tar.gz for Linux) to <Intel Quartus installation directory>/nios2eds/bin. The extraction will override files in <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2. 5. Verify the extraction is done correctly by making sure you see the <Intel Quartus installation directory>/nios2eds/bin/eclipse_nios2/plugin_customization.ini file 6. You can now launch Nios II SBT for Eclipse via eclipse-nios2.exe The instructions are included in the <Intel Quartus installation directory>/nios2eds/bin/README. This information will be included in the future release version of Intel® FPGA Software Installation and Licensing User Guide.
Why fcs_client app resulted in page allocation failure and unable to proceed when executing on Agilex™ 5 SoC FPGA Devices?
Description Due to a problem with limited HPS memory resources on the Agilex™ 5 FPGA device (e.g., when deploying it with 1GB RAM or less), kernel memory allocation failures may occur, particularly when invoking crypto services operations via the HPS on a system with fragmented memory. Memory fragmentation can result from repeated crypto services operations, prolonged system uptime, or other workloads that dynamically allocate and free memory. Resolution To work around this problem, consider that the crypto services driver requires 4MB of contiguous memory for each encryption/decryption transaction in the kernel. While tuning parameters such as min_free_kbytes may help by encouraging earlier flushing of buffers or caches, they do not guarantee the reservation of contiguous memory. The Contiguous Memory Allocator (CMA) is enabled in the system, and its reserved size can be increased through kernel boot arguments to improve robustness against fragmentation-related failures. Users and system integrators are responsible for ensuring that the operating system is configured to meet the memory requirements of their expected workloads. Failure to do so may result in degraded performance, application instability, or functional failures.Compiling an OpenCL kernel Using Both the --profile and -g0 Intel FPGA SDK for OpenCL Offline Compiler Command Options Does Not Remove Source Code from the .aocx File
Description When profiling your kernel, if you include both the -- profile and the -g0 Intel ® FPGA SDK for OpenCL™ Offline Compiler command options in your aoc command, the source code of your kernel and IP will still appear in the resulting .aocx file. Resolution You have two workaround options for removing the source code from existing .aocx files. To manually remove the source code: Run the aocl binedit <.aocx file> list command and find all sections that start with .acl.source or .acl.clang_ir . Run the aocl binedit <.aocx file> update <section> <null> command for every section identified in Step 1. For Windows, <null> is nul . For Linux, <null> is /dev/null . To remove the source code automatically using the Intel-provided Perl script: Download the Perl script (https://www.altera.com/en_US/pdfs/literature/rn/opencl_rn_attachments/strip_source.zip). Unzip the strip_source.zip file in the current working directory and then run the perl strip_source.pl <.aocx file> command. Note: To run the script on Windows, you must have Perl available on the command line. Ensure that you add the path to Perl to the PATH user environment variable setting.Intel® Arria® 10 FPGA PCIe 3.0 Endpoint is not compatible with PCIe 4.0 capable system.
Description The Intel® Arria® 10 FPGA PCIe 3.0 IP core will treat 4.0 Data Link Features Exchange as unsupported DLLP type (as per the PCIe 3.0 spec), unsupported DLLP type is not being flagged as valid DLLP, so does not ungate the InitFC. When this happens, no error is reported by the Intel® Arria® 10 FPGA. This is an expected behaviour. Resolution To work around this problem, disable the Data Link Feature Exchange in PCIe 4.0 system [Base spec 4.0 chapter 7.7.4.2 Data Link Feature Capabilities Register (Offset 04h)] to be compatible with legacy hardware. This problem will not be fixed in a future release of the Intel® Quartus® Prime Software.Why does the Synopsys VCS* simulator produce incorrect simulation results for Agilex™ 5 FPGAs?
Description The Agilex™ 5 FPGAs do not support the Synopsys VCS* two-step flow (compile and elaborate in one step and simulate in the next). You might see incorrect simulation results when simulating a multi-IP design with Synopsys VCS* simulator if you specify all IP and Quartus® simulation library source files using a single VCS command line, run_vcs. Resolution Follow these steps to use Synopsys VCS* simulator with VCS MX flow: Create design libraries using the mkdir command Compile all IP and Quartus® simulation library source files into their respective libraries using vlogan or vhdlan commands Elaborate the top-level design using the vcs command without specifying the source files compiled in Step 2 Simulate your design using the generated simv executable file The above steps are sometimes called VCS or VCS MX three-step flow (compile in one step, elaborate in the next step, and simulate in the final step). For information on which library files to be compiled, command examples, and command arguments, refer to the Platform Designer-generated VCS MX simulation setup script (/synopsis/vcsmx/vcsmx_setup. sh). If you were previously using the Platform Designer-generated VCS simulation setup script (/synopsys/vcs/vcs_setup.sh), switch to using the Platform Designer-generated VCS MX simulation setup script (/synopsys/vcsmx/vcsmx_setup.sh). Refer to Quartus® Prime Pro Edition User Guide: Third-party Simulation for more guidelines on incorporating the generated Synopsys VCS MX simulation scripts into a top-level project simulation setup script.Why does my Stratix® 10 device fail to configure if there is a delay between power up and configuration?
Description Due to a problem in the Stratix® 10 devices listed below, if it takes longer than 18 seconds from the completion of power up to the configuration of the first 256 Kb of configuration bitstream your Stratix® 10 device may fail to configure. The root cause lies in the Boot ROM, which causes a watchdog timer to overflow and causes the device to hang. This issue applies to all configuration schemes. Configuration via Protocol (CvP) is not impacted if the programming of the periphery meets the 18 seconds requirement as described in the workaround. This issue does not apply to reconfiguration. If you are using the FPGA Download Cable II and you encounter this issue, you will see the following error message: Error (20068): Configuration error, you must power-cycle the device to recover from this condition. To avoid this error, you must ensure that the device is configured within 18 seconds after completion of the power-on sequence. This issue affects the following Stratix 10 devices: Impacted Stratix 10 GX variants Stratix 10 GX 1100 H-Tile ES1 Stratix 10 GX 2800 H-Tile ES2 Stratix 10 GX 2800 H-Tile ES3 Stratix 10 GX 2800 L-Tile ES3 Stratix 10 GX 2500 L-Tile Production Stratix 10 GX 2800 L-Tile Production Impacted Stratix 10 SX variants Stratix 10 SX 1100 H-Tile ES1 Stratix 10 SX 2800 L-Tile ES1 Stratix 10 SX 2800 L-Tile ES2 Stratix 10 SX 2800 L-Tile ES3 Stratix 10 SX 2800 H-Tile ES3 Impacted Stratix 10 MX variants Stratix 10 MX 2100 H-Tile ES1 Impacted Stratix 10 TX variants Stratix 10 TX 2800 ES1 Stratix 10 TX 2100 ES1 Resolution The recommended conditions for configuration are shown in Figure 4 of the Stratix® 10 Configuration User Guide. After successful configuration the nSTATUS pin is driven high within 110 ms of nCONFIG pin transitioning to high. The observed behavior with impacted devices shows that the nSTATUS pin remains low until the device is power cycled. There are both hardware and software workarounds possible for this issue, which are described in the errata document. The hardware and software workarounds are common to all impacted Stratix® 10 device variants. To implement the software workaround, you are required to download and install patch 0.13 along with Quartus® Prime Pro Edition version 18.0 from the below links. Patch 0.13 Link (Microsoft Windows 10) : Download Patch 0.13 Link (Linux) : Download This problem is due to be fixed in the production version of the Stratix 10 SX 2800/2500 L-Tile device. If you are using an Stratix 10 GX 2800/2500 L-Tile device and a fix is required, move to the Stratix 10 SX 2800/2500 L-Tile device, which is drop-in compatible.Error (18212): Cannot load final snapshot for partition "root_partition”
Description Due to a problem in Intel® FPGA SDK for OpenCL™ version 19.1, you may see an OpenCL™ kernel compile crash after installing the Intel® Quartus® Prime Software 19.1 0.03 patch. The Intel® FPGA SDK for OpenCL™ uses BAK-cache (a local copy in a temporary folder of the local machine) to speed up subsequent kernel compiles. The error messages are shown below. It should be visible on the standard output and printed in quartus_sh_compile.log. Error (18212): Cannot load final snapshot for partition "root_partition" - the partition is not in a version compatible format. Error: Quartus Prime MIF/HEX Update was unsuccessful. 1 error, 0 warnings Error (23035): Tcl error: Error (23031): Evaluation of Tcl script scripts/post_flow_pr.tcl unsuccessful Resolution There are two ways to work around this problem Approach 1 (Recommended) Delete your local BAK cache. The problem will be solved for the next and all compiles onwards. For Windows, remove $ENV{'USERPROFILE'}\\AppData\\Local\\aocl For Linux, remove /var/tmp/aocl/$ENV{USERNAME} Approach 2 Run “aoc” argument with this option “-no-read-bsp-bak-cache”. Note this will slow down compile by an hour aoc -no-read-bsp-bak-cache <kernel> This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3.Why does FPGA configuration fail from HPS on Intel® Stratix®10 SX devices when I configure phase 2 bitstreams in HPS boot first mode?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3, phase 2 bitstream core.rbf configuration from HPS as part of an HPS boot first mode may fail for designs targeting Intel Stratix® 10 SX devices. The following errors may be seen: fpga_manager fpga0: Error while writing image data to FPGA failed to load fpga image OF: overlay: of_overlay_create: Pre-apply notifier failed (err=-110) create_overlay: Failed to create overlay (err=-110) Resolution This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 20.2 and onwards. To resolve this problem, download and install the latest device manager firmware for the Intel® Quartus® Prime Pro Edition Software 21.1/21.2/21.3/21.4/22.1/22.2/22.3. The latest device manager firmware versions are available from the following link: What is the latest device firmware for Intel® Agilex™ and Intel® Stratix® 10 devices?
