Why do Agilex® 5 FPGAs and Agilex® 3 FPGAs SEU report incorrect bits position within the frame and/or combination of row and frame index in the Quartus® Prime Pro Edition 25.1?
Description The total frame range for the Agilex® 5 FPGA and the Agilex® 3 FPGA devices is from bit0-bit12 (total 13 bits), while the maximum frame covered in the current Advanced SEU Detection IP, ASD IP, is from bit0-11(total 12 bits). The ASD IP frame range(12 bits) does not cover all the row and frame index combinations for the Agilex® 5 FPGA and the Agilex® 3 FPGA devices. This issue is also affecting the Fault Injection Debugger Tool, FID tool. As a result, the ASD IP and FID tool might report the incorrect bit position within the frame and/or the combination of row and frame index. Besides, you might not get an error when you read the Error Message Queue, although you have successfully injected the SEU error. You cannot insert SEU in the frame range between 1000- 1FFF. Instead, SEU error will be inserted in the frame range from 0- FFF. However, the SEU detection and correction are still fine for the entire bit and frame. Resolution To inject the SEU error to a pre-defined safe location: insert a safe SEU error with the mailbox command (INSERT_SAFE_SEU_ERROR 0x41) or the FID tool. Then, read the SEU with mailbox command (READ_SEU_ERROR 0x3C) or read the avst_seu_source_data signal of the ASD IP. Refer to the SEU Error Message Queue Bit Description in the SEU Mitigation User Guide: Agilex® 5 FPGAs and SoCs and Agilex® 3 FPGAs and SoCs to decode it. Note: Do not use READ_SEU_ERROR 0x3C mailbox command if your design contains the Advanced SEU Detection IP. Request a patch to inject into another location not listed in the pre-defined safe location. This is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.
drivers/src/altera_s10_mailbox_client.c:32:59: error: 'OS_FLAG_SET' undeclared (first use in this function); did you mean 'ALT_FLAG_SET'?
Description Due to a problem in Quartus® Prime Pro Edition Software, you might see an error when compiling Nios® V software with the Mailbox Client IP or 16550 Compatible UART Core driver, in FreeRTOS environment. This is because the driver software of the IP is using “MicroC/OS-II”-specific OS_* macros. Resolution The recommended macros are the OS-independent ALT_* macros. MicroC/OS-II Real-Time Operating System - Thread-Safe HAL Drivers FreeRTOS Real-Time Operating System - Thread-Safe HAL Drivers Replace the OS_* accordingly. MicroC/OS-II Macros Replace to OS_FLAG_SET ALT_FLAG_SET OS_FLAG_CLEAR ALT_FLAG_CLEAR OS_FLAG_WAIT_SET_ALL ALT_FLAG_WAIT_SET_ALL_WO_CONSUME (OS_FLAG_WAIT_SET_ALL + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ALL_WITH_CONSUME OS_FLAG_WAIT_SET_ANY ALT_FLAG_WAIT_SET_ANY_WO_CONSUME (OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME) ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME OS_FLAG_GRP* group ALT_FLAG_GRP(group)
Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why do the HPS Synopsys DesignWare APB timers fail to initialize in Linux* during the early boot stage in the FPGA HPS Embedded Software 25.1.1 and earlier?
Description Due to an inadequate configuration in the Linux* device tree node for the HPS Synopsys DesignWare APB timers in Agilex® 3, Agilex® 5, and Agilex® 7 FPGA devices, the timers remain in reset and fail to initialize during the early driver probe stages in FPGA HPS Embedded Software 25.1.1 and earlier. This problem is observed even when the timers are enabled through CONFIG_DW_APB_TIMER=y and CONFIG_DW_APB_TIMER_OF=y and enabled in the device tree. The root cause is that the timer driver is not a regular platform driver and does not support the probe/defer mechanism. The device tree timer nodes use a clock manager-dependent clock (clocks = <&clkmgr ...>; clock-names = "timer"), but the clock manager is not ready when the driver probes during early boot. As a result, timer initialization fails and the timers are unavailable during early boot. Resolution To work around this problem in FPGA HPS Embedded Software 25.1.1 and earlier, modify the clock configuration in each HPS timer node (timer0 through timer3) in the Linux device tree. Remove the clock manager reference (clocks and clock-names) and add clock-freq = <100000000> (100 MHz L4_SP clock). The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3 (FPGA HPS Embedded Software). Reference device trees in linux-socfpga use clock-freq instead of clocks/clock-names from the clock manager.Why does the ATF to Linux* Direct boot flow fail to boot from SD/eMMC in Quartus® Prime Pro version 25.1.1 and earlier when ATF is built with ARM* GCC compiler version 12.2 or higher on Agilex® 5 FPGA or Agilex® 3 FPGA devices?
Description Due to a problem in the optimization process of the ARM GCC compiler, versions 12.2 and higher, the Arm Trusted Firmware (ATF) SD/eMMC Cadence driver for Agilex® 5 FPGA and Agilex® 3 FPGA devices, in Quartus® Prime Pro Edition releases 25.1.1 and earlier, fails to send commands to SD cards or eMMC devices during the ATF to Linux Direct boot flow. The root cause is improper memory alignment of the ADMA2 descriptor address (requires 8-byte alignment for 64-bit addressing mode). GCC 12.2+ optimization introduces this misalignment. Resolution To work around this problem in Quartus Prime Pro Edition software version 25.1.1 and earlier, use one of the following options: In drivers/cadence/emmc/cdns_sdmmc.c, add __aligned(8) to the cdns_desc array for CONFIG_DMA_ADDR_T_64BIT. Build ATF with ARM GCC compiler version 11.3 or earlier. Disable optimizations when building ATF using CFLAGS="-O0" (may increase boot time). The problem has been fixed starting with Quartus Prime Pro Edition software version 25.3.Why does the INSERT_SAFE_SEU_ERROR command inject the SEU error into an incorrect location on Agilex® 3 FPGA devices?
Description Due to a problem with the Quartus® Prime Pro Edition Software version 25.3, injecting an SEU error using the INSERT_SAFE_SEU_ERROR command on Agilex® 3 FPGA devices may result in the READ_SEU_ERROR command reporting a location that does not match the predefined injection location. This incorrect SEU error location could potentially lead to functional errors in user designs. Resolution The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1,Why does compiling the PHY Lite for Parallel Interfaces IP example design for Agilex® 3 FPGA C-Series and Agilex® 5 FPGA E-Series and D-Series generate invalid Fitter assignment warnings?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see that the PHY Lite for Parallel Interfaces IP example design compilations for Agilex® 3 FPGA C-Series and Agilex® 5 FPGA E-Series and D-Series generate a warning message on invalid Fitter assignments. The following assignments are invalid and listed in the Ignored Assignments panel in the Fitter Compilation Report: Can Relax Periphery to Core Hyper Register Constraint TOP_FEEDBACK_DELAY_STEP TOP_FEEDBACK_DELAY_SEL BOT_FEEDBACK_DELAY_STEP BOT_FEEDBACK_DELAY_SEL Resolution There is no workaround for this problem in the Quartus® Prime Pro Edition Software version 25.3. The invalid assignments can safely be ignored. The compilation and simulation results are valid. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3.1.Error: Unknown option: -port_type while execute set_instance_assignment with the option
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and 25.1.1, you might see this error when running a "set_instance_assignment" with -port_type option e.g. Error:Unknown option: -port_type Error:--------------------------------------------------------------------------- Error:Usage: set_instance_assignment [-h] [-help] [-long_help] [-comment <comment>] [-disable] [-entity <entity_name>] [-fall] [-from <source>] -name <name> [-remove] [-rise] [-section_id <section id>] [-tag <data>] [-to <destination>] [<value>] Error: -h: Quick usage Error: -help: Short help Error: -long_help: Long help with examples and possible return values Error: -comment <comment>: Comment Error: -disable: Option to disable assignment Error: -entity <entity_name>: Entity to which to add assignment Error: -fall: Option applies to falling edge Error: -from <source>: Source of assignment Error: -name <name>: Assignment name Error: -remove: Option to remove assignment Error: -rise: Option applies to rising edge Error: -section_id <section id>: Section id Error: -tag <data>: Option to tag data to this assignment Error: -to <destination>: Destination of assignment Error: <value>: Assignment value Error:--------------------------------------------------------------------------- Error: while executing Error:"set_instance_assignment -name DUPLICATE_SYNC_FANIN …" Resolution A patch is available to fix this problem in the Quartus Prime Pro Edition Software version 25.3. Download and install patch 0.24 below. A patch is available to fix this problem in the Quartus Prime Pro Edition Software version 25.1.1. Download and install patch 1.49 below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why do I see a large timing violation when using the IOPLL IP’s Non-Dedicated Feedback Path option?
Description A timing violation may occur when the Non-Dedicated Feedback Path option is enabled in the IOPLL IP. This is caused by the C-counter starting to toggle unexpectedly, resulting in a phase shift of the output clocks relative to the input clock. This problem affects the following device families: Stratix® 10 FPGAs Agilex® 3 FPGAs Agilex® 5 FPGAs Agilex® 7 FPGAs Resolution To address this timing violation, add multi-cycle constraints to the impacted timing paths. 1) The set_multicycle_path constraint should only be applied to the affected path. 2) The affected clock domain can be either the source or the destination clock domain in the timing transfers that this behavior may impact.