Why is there a failure in the design if we are doing design migration for Agilex™ 3/ Agilex™ 5 FPGA from the Quartus® Prime Pro Edition software version 25.1.1 to 25.3?

Description

Due to new implementation of the input reference clock buffer protection, there are additional ports being added in the reset sequencer IP, and some of the ports are being renamed from the Quartus® Prime Pro Edition software version 25.1.1 to 25.3. User will need to update the RTL with the updated ports name, if they have GTS Reset Sequencer IP ports connected to their IPs. 

Resolution

For a workaround, users will require to update the existing port name to the new ports that are available in the Reset Sequencer IP. The existing ports that will require update will be: 

• i_refclk_bus_out (in 25.1.1) --> i_src_rs_refclk_status_bus_out (in 25.3) 
• o_shoreline_refclk_fail_stat (in 25.1.1) --> o_refclk_fail_status (in 25.3)