Recent Content
Why cant my USB Blaster III Development cable program in active serial through Quartus Programmer?
Description Due to a firmware issue the USB Blaster III Development cable may not have the correct product ID and may inadvertently disabled the active serial programming feature. Resolution To resolve this issue the Product ID of the cable should be updated to (6023). Perform the following steps on Windows to update the ID. Download and Install the FT_PROG.exe the EEPROM Programming Utility from FTDI https://ftdichip.com/utilities/ Plug-in your USB Blaster III development cable into your computer. Uninstall the USB Blaster III device driver from the device manager. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right Click on the USB Blaster III device and Click Uninstall. Tick "Attempt to delete the driver for this device" or "Delete the driver software for this device" during uninstallation. This prevents the UB3 driver from being automatically reinstalled. Install the FTDI Device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Blaster III devices. To Identify the correct USB Blaster III device Right click on each USB Blaster III device and click Properties. Find USB Blaster III device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click Let me pick from a list of available drivers on my computer. If, Select your device’s type from the list below, choose Universal Serial Bus controllers. When selecting a driver click the FTDI manufacturer then select USB Serial Converter A Version: 2.12.36.4 and click the Next button. Program your USB Blaster III Development Cable with FT_PROG.exe to update your product ID. Open the FT_PROG.exe from FTDI installed in step 1. From the DEVICES menu click Scan and Parse to bring up your USB Blaster III Device Under the Device Tree select the section called USB Device Descriptor This should contain a property called Product ID and should have a value of 6023, change this to 6023 if it is not set to this value. Once changed, under the DEVICES menu click Program to flash the EEPROM Uninstall the FTDI driver installed in step 4. Open the Windows Device Manager. Find the group Universal Serial Sub controllers In the Universal Serial Bus controllers right click on the USB Serial Converter A and Click Uninstall. Do not tick "Attempt to delete the driver for this device" or "Delete the driver software for this device". Re-Install the USB Blaster III device driver. Open the Windows Device Manager. Find the group called Other Devices. In the group Other Devices there may be several USB Serial Port devices or USB Blaster III devices. To Identify the correct USB Serial Port device Right click on each USB Serial Port device and click Properties. Find USB Serial Port device that contains values that end with MI_00 Once Identified, Right click on correct USB Blaster III device and click Update driver To Update driver click Browse my computer for drivers Search and select the USB Blaster III driver directory under your Quartus installation. <Quartus Path>\qdrivers\quartus\drivers\usb-blaster-iii Click the Next button. Windows should show USB Blaster III driver installed. Verify USB Blaster III device has the correct Product ID. Open the Windows Device Manager. Find the group called JTAG cables, under this group there should be a USB Blaster III device. Right click on each USB Blaster III device and click Properties. Values should contain PID_6023 in the string, if not unplug and re-plugin the device. Open Quartus Programmer and Validate that the Active Serial programing is now available.Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration?
Description HVIO PLL reconfiguration may require word-addressed register offsets for Agilex® 5 FPGA and Agilex® 3 FPGA devices. The HVIO PLL reconfiguration registers for Agilex 5 and Agilex 3 devices are documented using byte offsets, but the Avalon® Memory‑Mapped (Avalon‑MM) interface expects word-addressed offsets. Using the documented byte offsets directly on the address bus can cause incorrect register access, which prevents the PLL from recovering after it loses lock during reconfiguration. Resolution Apply the following workaround to ensure correct HVIO PLL reconfiguration: Use word-addressed offsets when accessing HVIO PLL registers through the Avalon-MM interface. Convert documented byte offsets to word offsets by dividing by 4 before driving the address bus. Update the register address mapping in your design accordingly. Example: localparam [8:0] ENABLE_RW_ADDR = 9'h10 >> 2; // 0x04 localparam [8:0] ENABLE_RECAL_ADDR = 9'h48 >> 2; // 0x12 localparam [8:0] CLK_GATING_ADDR = 9'h54 >> 2; // 0x15 localparam [8:0] CLEAR_STATUS_ADDR = 9'h58 >> 2; // 0x16 localparam [8:0] C0_ADDR = 9'h5C >> 2; // 0x17 localparam [8:0] C1_ADDR = 9'h60 >> 2; // 0x18 localparam [8:0] RESET_ADDR = 9'h80 >> 2; // 0x20 localparam [8:0] RECAL_ADDR = 9'h88 >> 2; // 0x22Internal Error: Sub-system: BITASM, File: /quartus/pgm/bitasm/bitasm_update_main_descriptor.cpp, Line: 180. OPN Specification U is not mapped to SKUID
Description Due to a problem in Quartus® Prime Pro Edition Software version 26.1, you may see this internal error when trying to provision a root key (.qky) or AES root key compact certificate (.ccert) into an Agilex® 3 FPGA device. Resolution To work around this problem, generate a helper image (.rbf) for your specific Agilex® 3 FPGA variant and configure the FPGA with the generated helper image prior to provisioning the .qky or .ccert file. For example : quartus_pfg --helper_image -o helper_device=A3CY100BM16A -o subtype=PROVISION provision_helper.rbf quartus_pgm -c<n> -mjtag -o "p;provision_helper.rbf" --force quartus_pgm -c<n> -mjtag -o "p;root.qky" This problem will be fixed in a future release of the Quartus® Prime Pro Edition software.Internal Error: Sub-system: RTM, File: /quartus/tsm/rtm/rtm_min_cost_flow_retimer.cpp, Line: 3097 Cost-scaling is not supported yet.
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you may see the this internal error during the Fitter stage. Resolution To work around this problem, disable the Early Retimer by adding this QSF assignment: set_global_assignment -name FITTER_EARLY_RETIMING OFF This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.Why are there intermittent calibration failures in the External Memory Interfaces Agilex® 5 FPGA E-Series IP?
Description Due to a problem in Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you may run into intermittent EMIF calibration failures on LPDDR4 1CHx32, 2-Rank configurations running at 1333 MHz on Agilex® 5 FPGA E Series devices. Resolution To work around this problem, disable cross-rank delay averaging by enabling the following debug flag in the parameter table: DBG_CFG_DISABLE_RANK_AVG_AND_OVR This prevents the firmware from averaging DQS-WR delays across ranks, which eliminates the invalid delay setting that causes the MGN-stage calibration failure. Note: Disabling rank averaging may affect traffic stability in some configurations. A patch is available to fix this problem in Quartus Prime Pro Edition Software version 25.3.1. Download and install the below 1.04 patch. This problem has been fixed beginning with version 26.1 of the Quartus Prime Pro Edition Software.Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why is Agilex® 5 and Agilex® 3 FPGA External Memory Interfaces (EMIF) IP missing from the BSP Linker when the Nios® V processor Board Support Package is generated?
Description Due to a problem in the Quartus ® Prime Pro Edition starting since software version 24.1, the Agilex ® 5 and Agilex ® 3 FPGA EMIF IP is missing from the BSP Linker when generating the Board Support Package. This might occur for Nios ® V processor designs targeting Agilex 5 FPGA or Agilex 3 FPGA, that uses EMIF IP. This is because Agilex 5 and Agilex 3 FPGA EMIF IP are missing the isMemoryDevice agent information. Refer to Nios® V Processor Software Developer Handbook - Memory-Mapped Slave Information (PDF) for information about isMemoryDevice agent information. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 5 FPGAs and SoCs (PDF) for information Agilex ® 5 FPGA EMIF IP. Refer to External Memory Interfaces (EMIF) IP User Guide Agilex® 3 FPGAs and SoCs (PDF) for information Agilex ® 3 FPGA EMIF IP. Resolution To work around this problem in the Quartus ® Prime Pro Edition in all the affected software version, apply either one of the following workarounds: Workaround 1: Manually add isMemoryDevice to the EMIF IP (in Platform Designer only) Select the s*_axi4 signal (mainband AXI4 from fabric to controller) that connects to the Nios ® V processor’s instruction/data manager. Right-click, and click Edit Component Instantiation ... Select s*axi4 and edit the Assignments. Enter new Key as embeddedsw.configuration.isMemoryDevice, and Value as 1. Save the new assignment. Generate a new BSP. Workaround 2: Manually define EMIF IP linker memory device Refer to the Nios V Embedded Processor Design Handbook - Defining Address Span Extender Linker Memory Device. The example demonstrates how to manually define Address Span Extender linker memory device. For this problem, apply the same procedure but on the EMIF IP directly. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software. Related Articles LPDDR4 not available in NIOS® V/g linker script - Agilex® 5 FPGA, Quartus® 26.1 Pro Issue with BSP Creation for Nios® V/m Using LPDDR4 on Agilex® 5 FPGA (Quartus® 24.1 & 24.3.1)Why does the GTS AXI Multichannel DMA IP for PCI Express* IP send Completion Data (CplD) with a length exceeding the Maximum Payload Size (MPS) set?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, the GTS AXI Multichannel DMA IP for PCI Express* IP sends Completion with Data (CplD) lengths that exceed the negotiated Maximum Payload Size (MPS) set. Resolution Patches are available to fix this problem for the Quartus Prime Pro Edition Software version 26.1 versions. Download and install patch below. Quartus Prime Pro Edition Software v26.1 Patch 0.20 This problem is currently scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.
