Altera_Forum
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Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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22 Replies
Altera_Forum--- Quote Start --- Does altera fpga support inbuilt analog to digital converter?? --- Quote End --- At the system level, an ADC is sending parallel data at a predefined rate, there's no particular support needed for it. Some Altera Dev Kits have high speed ADC, they just send the data in parallel. Slow ADC usually have serial interfaces, e.g. SPI. You have to convert the serial data to parallel. In my view, a SPI interface isn't more than a few lines of VHDL code, I don't expect particluar support for it. You could however use the audio codec supplied with several Dev Kits, e.g. Terasic DE2 to convert the input signal. The demonstration code for the respective boards basically shows how to use the converter (but not in a really instructive way). The sense of processing an analog 60 Hz input signal strongly depends on the overall system function. If you only need the fundamental frequency and phase information, a bandpass filter with a succeeding comparator feeding a digital phase detector can do the same. If the analog input is however used for other purposes (measurement, control of grid tied inverter) it's most simple to feed the analog waveform to the PLL.- Altera_Forum
Thank u so much for your reply. I am bit confused by your answer, since i am new to altera.
I have an analog input signal of 60 Hz. I should lock the input signal with same phase and frequency and get the output in digital form. I should multiply the output(digital pulse with 60 HZ) to get in MHz. Then i should perform pulse width modulation based on the sine wave table and the final pulse i should feed in inverter. This is my overall task. Should i give the analog input signal of 60 Hz in 40 pin input/output port . Then by using vhdl code i should convert 60 HZ analog to digital. - Altera_Forum
I'm not sure, if you necessarily need a PLL for synchronizing a PWM generator to a 60 Hz input. If the 60 Hz input is from the mains power line, the frequency variations will be very low. So generating the PWM timing from a crystal and only synchronizing it to the 60 Hz reference should be sufficient.
- Altera_Forum
The frequency variations will be very low. To get exact pwm with reference to the input , pll is needed.
I just want to know how to convert my analog input to digital . it can be implemented only vhdl code or any other inbuilt adc is available in altera fpga. Your help is really appreciated - Altera_Forum
No Altera FPGA has built-in ADC. As I mentioned, some development kits have an ADC, but because of the large range of differenr requirements and different available devices, designer use to select them according to the application.
--- Quote Start --- To get exact pwm with reference to the input , pll is needed. --- Quote End --- I don't generally agree. But many inverter control concepts are possible. - Altera_Forum
Since my input is in 60 Hz will below PDF block diagram works for me to get synchronization of the input.
http://users.ece.gatech.edu/~jskenney/l080-adpll(2up).pdf (http://users.ece.gatech.edu/%7ejskenney/l080-adpll%282up%29.pdf) file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot.jpg In attached pdf on (page file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot-1.jpg 080-18) example 1 . Kindly help me - Altera_Forum--- Quote Start --- Since my input is in 60 Hz will below PDF block diagram works for me to get synchronization of the input. http://users.ece.gatech.edu/~jskenney/l080-adpll(2up).pdf (http://users.ece.gatech.edu/%7ejskenney/l080-adpll%282up%29.pdf) In attached pdf on (page 080-18) example 1 . Kindly help me
- Altera_Forum
Sounds like a fun project. Generally, the PLL phase detector types are chosen for their characteristics in an analog PLLs. For a digital PLL you can implement whatever works in your design. If you have an ADC input, you will have to use an average of the input for the zero crossing. If you are using a comparitor, the input will be a simple zero or one. These outputs can be further filtered to reduce noise. From these inputs you can implement the logic of any of the phase detector types.
Texas instruments has some documentation on their sn74ls297, which is a diigital PLL part. This is really a control problem and should be properly characterized as such. Especially you if you need zero phase difference between the input/output. - Altera_Forum--- Quote Start --- will below PDF block diagram works for me to get synchronization of the input --- Quote End --- Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals.
- Altera_Forum--- Quote Start --- Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals. --- Quote End --- So instead of Jk flip flop , i can go ahead with XOR PHASE-DETECTOR right? My input is 60 Hz (variable) analog signal. In the block diagram i have few questions, since my input is 60 HZ 1. how i should choose my fC(INPUT to variable N counter) 2. Can explain the digital controlled oscillator part? Ur help is really appreciated.
