Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- will below PDF block diagram works for me to get synchronization of the input --- Quote End --- Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals.
