Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorNo Altera FPGA has built-in ADC. As I mentioned, some development kits have an ADC, but because of the large range of differenr requirements and different available devices, designer use to select them according to the application.
--- Quote Start --- To get exact pwm with reference to the input , pll is needed. --- Quote End --- I don't generally agree. But many inverter control concepts are possible.
