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Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorI'm not sure, if you necessarily need a PLL for synchronizing a PWM generator to a 60 Hz input. If the 60 Hz input is from the mains power line, the frequency variations will be very low. So generating the PWM timing from a crystal and only synchronizing it to the 60 Hz reference should be sufficient.
