Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals. --- Quote End --- So instead of Jk flip flop , i can go ahead with XOR PHASE-DETECTOR right? My input is 60 Hz (variable) analog signal. In the block diagram i have few questions, since my input is 60 HZ 1. how i should choose my fC(INPUT to variable N counter) 2. Can explain the digital controlled oscillator part? Ur help is really appreciated.
