CYCLONE IVE ODDR delay mismatch

Hello Altera Experts!

I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec.

I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses.