Forum Discussion
Occasional ContributorCYCLONE IVE ODDR delay mismatch
The routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
Occasional ContributorIf you look at the first 2 lines you will notice that the 'data delay' value is about 1 nanosecond greater than all the other lines. Using the ODDRs I expected differences on the order of 100-200 picoseconds between all the pins. This is what I can't understand.
ShengN_alteraSuper Contributor
The timing slack is positive for all paths meaning the design meets timing requirements. The difference you are seeing in the Data Delay column does not indicate a functional problem. This variation is related to the physical routing inside the FPGA.
Quartus always attempts to use the shortest and fastest routing resources first. In your case, the majority of the DAC output signals were able to use these optimal routes, resulting in very closely matched delays. For the first two channels, however, those preferred routing paths were no longer available due to normal placement and congestion conditions. As a result, Quartus selected alternative routing tracks, which are slightly longer and therefore contributed to the additional ~1 ns of data delay.
This behavior is expected and common when multiple high‑speed output signals originate from the same clock source but fan out across different I/O locations. The additional delay on the first two lines is due to longer routing, best routing path had been used up. But you can rest assure about the functional because all paths are positive slacks and timing is fully met.
