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GOMEZ_IT
Occasional Contributor
Occasional ContributorCYCLONE IVE ODDR delay mismatch
Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultane...
The routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
GOMEZ_ITOccasional Contributor
Occasional ContributorHi Sheng. Can you share the timing analisys from Pll1/clk0 clock to clk_dac_a or clk_dac_b clocks?
ShengN_alteraSuper Contributor
Here is the timing:
There's no problem as well.
