Forum Discussion
Occasional ContributorCYCLONE IVE ODDR delay mismatch
The routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
Occasional ContributorDo you think it is possible to force Quartus to use the same type of routing (the fast one) used on all the other pins? I am aware that at the moment the timing is being exceeded, but right now if I wanted to increase the clock frequency I would have limitations precisely due to those 2 "slower" pins.
Super ContributorThe routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
