Forum Discussion
Occasional ContributorCYCLONE IVE ODDR delay mismatch
The routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
New ContributorThat's right, the OP's original assumption was correct. Different types of dual-purpose pins have different propagation delay. I can't see this clearly stated in any documentation, but it definitely seems so. For the types above, identified by pin number, the varying part is as follows:
- 105: 4.393 ns
- 103: 3.281 ns
- 110: 3.128 ns
So if you want to do a source-synchronous interface with as little data skew as possible, make sure all your data bits are driven from the same type of I/Os. At least avoid the VREF ones.
On a side note, the slack mentioned above seems to refer to the falling edge of the launch clock to the rising edge of the latch clock. I think that is a false path, the data is only meant to change on rising edges. So the slack is actually better by 5 ns, but if you really need to run as fast a possible you need to reduce that data skew.
