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GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
26 days ago
Solved

CYCLONE IVE ODDR delay mismatch

Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultane...
Timing
  • ShengN_altera's avatar
    ShengN_altera
    17 days ago

    The routing delay difference due to different type of pin assigned.

    The bit fpga_dac_CHA[3] using this type of pin:

     

     

    While other bits using these type of pin:

     

     

    Different pin type will have different internal routing delay and this is fix one which cannot be changed.

    So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:

     

GOMEZ_IT's avatar
GOMEZ_IT
Icon for Occasional Contributor rankOccasional Contributor
18 days ago

Do you think it is possible to force Quartus to use the same type of routing (the fast one) used on all the other pins? I am aware that at the moment the timing is being exceeded, but right now if I wanted to increase the clock frequency I would have limitations precisely due to those 2 "slower" pins.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
17 days ago

Try cross-probing from the timing analysis report to the Chip Planner (right-click the path and go to Locate Path).  This might help identify why the internal routing is longer for these 2 paths.