Forum Discussion
Occasional ContributorCYCLONE IVE ODDR delay mismatch
The routing delay difference due to different type of pin assigned.
The bit fpga_dac_CHA[3] using this type of pin:
While other bits using these type of pin:
Different pin type will have different internal routing delay and this is fix one which cannot be changed.
So if change bit fpga_dac_CHA[3] and fpga_dac_CHB[3] pins to for example PIN_115 and PIN_120. The timing will be similar for all bits:
Occasional ContributorI'm still unsure about the false path issue. I can't figure out why I should disable the path between the falling edge of launch-clk and the rise edge of latch-clk. The launch-clk for oddrs could also be the falling one, since it's a ddr.
cblixt1New Contributor
Yes, but you are using the DDR flipflops just to minimize the skew. You are not planning to output DDR data, you will supply the same indata for both edges. Quartus doesn't know this, so you have to tell it using this constraint.
ShengN_alteraSuper Contributor
I believe cblixt1 is talking about the source synchronous constraint. You may refer to this link https://docs.altera.com/v/u/docs/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces
