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Altera_Forum's avatar
Altera_Forum
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15 years ago

Phase lock loop

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank u so much for your reply. I am bit confused by your answer, since i am new to altera.

I have an analog input signal of 60 Hz. I should lock the input signal with same phase and frequency and get the output in digital form. I should multiply the output(digital pulse with 60 HZ) to get in MHz. Then i should perform pulse width modulation based on the sine wave table and the final pulse i should feed in inverter. This is my overall task.

Should i give the analog input signal of 60 Hz in 40 pin input/output port .

Then by using vhdl code i should convert 60 HZ analog to digital.