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Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorSounds like a fun project. Generally, the PLL phase detector types are chosen for their characteristics in an analog PLLs. For a digital PLL you can implement whatever works in your design. If you have an ADC input, you will have to use an average of the input for the zero crossing. If you are using a comparitor, the input will be a simple zero or one. These outputs can be further filtered to reduce noise. From these inputs you can implement the logic of any of the phase detector types.
Texas instruments has some documentation on their sn74ls297, which is a diigital PLL part. This is really a control problem and should be properly characterized as such. Especially you if you need zero phase difference between the input/output.
