Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Does altera fpga support inbuilt analog to digital converter?? --- Quote End --- At the system level, an ADC is sending parallel data at a predefined rate, there's no particular support needed for it. Some Altera Dev Kits have high speed ADC, they just send the data in parallel. Slow ADC usually have serial interfaces, e.g. SPI. You have to convert the serial data to parallel. In my view, a SPI interface isn't more than a few lines of VHDL code, I don't expect particluar support for it. You could however use the audio codec supplied with several Dev Kits, e.g. Terasic DE2 to convert the input signal. The demonstration code for the respective boards basically shows how to use the converter (but not in a really instructive way). The sense of processing an analog 60 Hz input signal strongly depends on the overall system function. If you only need the fundamental frequency and phase information, a bandpass filter with a succeeding comparator feeding a digital phase detector can do the same. If the analog input is however used for other purposes (measurement, control of grid tied inverter) it's most simple to feed the analog waveform to the PLL.
