I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???

You didn't mention the intended output of the PLL (frequency, waveform). In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. In contrast to the high frequency analog PLL provided for FPGA clocking, the complete PLL function is performed by digital signal processing. Thus it's called digital or all digital PLL (DPLL/ADPLL).

My output should be same as input(60 HZ). But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized. I was trying to implement in zero buffer mode using a[/U][/U]ltpll megafunction But its input range is in MHz. It is possible for me to implement in fpga reconfig methods.

--- Quote Start --- But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized. --- Quote End --- How do you want to achieve synchronization? Did you notice the PLL input frequency range? Minimum input frequency, set by the PFD properties, is 10 MHz. That's why I suggested an ADPLL design.

Thank u so much for the reply. it is possible for me to implement ADPLL in fpga, using megafunction wizard? If not , can we code in vhdl. Your help is appreciated..

There's no Altera MegaFunction providing ADPLL functionality. There has been a previous forum discussion related to an ADPLL code sourced from Best's PLL text book, if I understand right. The original poster said it doesn't work. Apart from this particular code, it's of course possible to implement the ADPLL concept from literature in VHDL. I have implemented a PLL as sketched in my above post. But it's part of a larger customer design and neither dedicated to the public domain nor written to be instructive. http://www.alteraforum.com/forum/showthread.php?t=3310

Phase lock loop | Altera Community

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Altera_Forum
Honored Contributor
14 years ago
Hi i am implementing phase lock loop in altera cyclone II. I wrote my code in vhdl. My input is 60 Hz analog signal, here are my questions,

1. How i should convert 60 Hz analog to digital signal using vhdl coding?

2. I implemented phase detected and its perfectly finding the phase error and loop filter is also working well finding the measure of phase error.
The above two i have implemented in two process.
Now comes the difficult situation, when i am using the clock in third process which is digital controlled oscillator, it says that " couldn't implement registers for assignments on this clock edge " . How i should solve this error ???

i tested phase detected and loop filter using 60 Hz digital signal. I want to know converting digital to analog using vhdl coding?
Altera_Forum
Honored Contributor
14 years ago
1) you can't do that with just VHDL. You need an external ADC chip.
2) it depends on how you coded your process. Having both rising and falling edges conditions in the same process can produce that error.

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Phase lock loop

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